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PCI: designware: Swap order of dw_pcie_writel_unroll() reg/val arguments
Swap order of dw_pcie_readl_unroll() arguments to match the "dev, pos, val" order used by pci_write_config_word() and other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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@ -164,8 +164,8 @@ static u32 dw_pcie_readl_unroll(struct pcie_port *pp, u32 index, u32 reg)
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return dw_pcie_readl_rc(pp, offset + reg);
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}
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static void dw_pcie_writel_unroll(struct pcie_port *pp, u32 index,
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u32 val, u32 reg)
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static void dw_pcie_writel_unroll(struct pcie_port *pp, u32 index, u32 reg,
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u32 val)
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{
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u32 offset = PCIE_GET_ATU_OUTB_UNR_REG_OFFSET(index);
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@ -196,20 +196,20 @@ static void dw_pcie_prog_outbound_atu(struct pcie_port *pp, int index,
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u32 retries, val;
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if (pp->iatu_unroll_enabled) {
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dw_pcie_writel_unroll(pp, index,
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lower_32_bits(cpu_addr), PCIE_ATU_UNR_LOWER_BASE);
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dw_pcie_writel_unroll(pp, index,
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upper_32_bits(cpu_addr), PCIE_ATU_UNR_UPPER_BASE);
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dw_pcie_writel_unroll(pp, index,
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lower_32_bits(cpu_addr + size - 1), PCIE_ATU_UNR_LIMIT);
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dw_pcie_writel_unroll(pp, index,
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lower_32_bits(pci_addr), PCIE_ATU_UNR_LOWER_TARGET);
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dw_pcie_writel_unroll(pp, index,
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upper_32_bits(pci_addr), PCIE_ATU_UNR_UPPER_TARGET);
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dw_pcie_writel_unroll(pp, index,
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type, PCIE_ATU_UNR_REGION_CTRL1);
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dw_pcie_writel_unroll(pp, index,
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PCIE_ATU_ENABLE, PCIE_ATU_UNR_REGION_CTRL2);
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dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_LOWER_BASE,
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lower_32_bits(cpu_addr));
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dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_UPPER_BASE,
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upper_32_bits(cpu_addr));
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dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_LIMIT,
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lower_32_bits(cpu_addr + size - 1));
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dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_LOWER_TARGET,
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lower_32_bits(pci_addr));
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dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_UPPER_TARGET,
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upper_32_bits(pci_addr));
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dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_REGION_CTRL1,
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type);
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dw_pcie_writel_unroll(pp, index, PCIE_ATU_UNR_REGION_CTRL2,
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PCIE_ATU_ENABLE);
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} else {
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dw_pcie_writel_rc(pp, PCIE_ATU_VIEWPORT,
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PCIE_ATU_REGION_OUTBOUND | index);
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