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arm64: dts: ls1012a: Add QSPI node properties
Add support for QSPI on NXP layerscape LS1012A-RDB, LS1012A-QDS, LS1012A-FRDM and LS1012A-FRWY boards. LS1012A-RDB has 2 Spansion "s25fs512s" flashes of size 64M each and only one can be accessed at a time. LS1012A-QDS/FRDM has 1 spansion "s25fs512s" flash of size 64M. LS1012A-FRWY has one winbond "w25q16dw" flash of size 2M. Use generic compatibles as "jedec,spi-nor" for automatic detection of flash. Configure RX and TX buswidth values as 2 as only two I/O lines are available for data transfer. Add ls1012a(si) node alongwith flash nodes. Signed-off-by: Ashish Kumar <Ashish.kumar@nxp.com> Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -74,6 +74,21 @@ codec: sgtl5000@a {
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};
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};
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&qspi {
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status = "okay";
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s25fs512s0: flash@0 {
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compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <50000000>;
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m25p,fast-read;
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reg = <0>;
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spi-rx-bus-width = <2>;
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spi-tx-bus-width = <2>;
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};
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};
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&sai2 {
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status = "okay";
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};
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@ -23,3 +23,18 @@ &duart0 {
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&i2c0 {
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status = "okay";
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};
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&qspi {
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status = "okay";
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w25q16dw0: flash@0 {
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compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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m25p,fast-read;
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spi-max-frequency = <50000000>;
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reg = <0>;
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spi-rx-bus-width = <2>;
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spi-tx-bus-width = <2>;
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};
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};
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@ -128,6 +128,21 @@ codec: sgtl5000@a {
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};
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};
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&qspi {
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status = "okay";
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s25fs512s0: flash@0 {
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compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <50000000>;
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m25p,fast-read;
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reg = <0>;
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spi-rx-bus-width = <2>;
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spi-tx-bus-width = <2>;
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};
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};
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&sai2 {
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status = "okay";
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};
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@ -35,6 +35,21 @@ &i2c0 {
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status = "okay";
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};
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&qspi {
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status = "okay";
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s25fs512s0: flash@0 {
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compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <50000000>;
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m25p,fast-read;
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reg = <0>;
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spi-rx-bus-width = <2>;
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spi-tx-bus-width = <2>;
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};
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};
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&sata {
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status = "okay";
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};
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@ -137,6 +137,19 @@ soc {
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#size-cells = <2>;
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ranges;
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qspi: spi@1550000 {
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compatible = "fsl,ls1021a-qspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x1550000 0x0 0x10000>,
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<0x0 0x40000000 0x0 0x10000000>;
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reg-names = "QuadSPI", "QuadSPI-memory";
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interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "qspi_en", "qspi";
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clocks = <&clockgen 4 0>, <&clockgen 4 0>;
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status = "disabled";
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};
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esdhc0: esdhc@1560000 {
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compatible = "fsl,ls1012a-esdhc", "fsl,esdhc";
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reg = <0x0 0x1560000 0x0 0x10000>;
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