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[PATCH] ppc32: Support 36-bit physical addressing on e500
To add support for 36-bit physical addressing on e500 the following changes have been made. The changes are generalized to support any physical address size larger than 32-bits: * Allow FSL Book-E parts to use a 64-bit PTE, it is 44-bits of pfn, 20-bits of flags. * Introduced new CPU feature (CPU_FTR_BIG_PHYS) to allow runtime handling of updating hardware register (SPRN_MAS7) which holds the upper 32-bits of physical address that will be written into the TLB. This is useful since not all e500 cores support 36-bit physical addressing. * Currently have a pass through implementation of fixup_bigphys_addr * Moved _PAGE_DIRTY in the 64-bit PTE case to free room for three additional storage attributes that may exist in future FSL Book-E cores and updated fault handler to copy these bits into the hardware TLBs. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Kumar Gala
Linus Torvalds
parent
b464fce5ed
commit
f50b153b19
@ -98,13 +98,19 @@ config FSL_BOOKE
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config PTE_64BIT
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bool
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depends on 44x
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default y
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depends on 44x || E500
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default y if 44x
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default y if E500 && PHYS_64BIT
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config PHYS_64BIT
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bool
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depends on 44x
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default y
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bool 'Large physical address support' if E500
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depends on 44x || E500
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default y if 44x
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---help---
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This option enables kernel support for larger than 32-bit physical
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addresses. This features is not be available on all e500 cores.
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If in doubt, say N here.
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config ALTIVEC
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bool "AltiVec Support"
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@ -347,6 +347,38 @@ skpinv: addi r6,r6,1 /* Increment */
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mtspr SPRN_SRR1,r3
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rfi /* change context and jump to start_kernel */
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/* Macros to hide the PTE size differences
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*
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* FIND_PTE -- walks the page tables given EA & pgdir pointer
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* r10 -- EA of fault
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* r11 -- PGDIR pointer
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* r12 -- free
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* label 2: is the bailout case
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*
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* if we find the pte (fall through):
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* r11 is low pte word
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* r12 is pointer to the pte
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*/
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#ifdef CONFIG_PTE_64BIT
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#define PTE_FLAGS_OFFSET 4
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#define FIND_PTE \
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rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
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lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
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rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
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beq 2f; /* Bail if no table */ \
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rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
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lwz r11, 4(r12); /* Get pte entry */
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#else
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#define PTE_FLAGS_OFFSET 0
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#define FIND_PTE \
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rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \
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lwz r11, 0(r11); /* Get L1 entry */ \
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rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \
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beq 2f; /* Bail if no table */ \
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rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \
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lwz r11, 0(r12); /* Get Linux PTE */
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#endif
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/*
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* Interrupt vector entry code
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*
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@ -405,13 +437,7 @@ interrupt_base:
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mfspr r11,SPRN_SPRG3
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lwz r11,PGDIR(r11)
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4:
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rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
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lwz r11, 0(r11) /* Get L1 entry */
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rlwinm. r12, r11, 0, 0, 19 /* Extract L2 (pte) base address */
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beq 2f /* Bail if no table */
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rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
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lwz r11, 0(r12) /* Get Linux PTE */
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FIND_PTE
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/* Are _PAGE_USER & _PAGE_RW set & _PAGE_HWWRITE not? */
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andi. r13, r11, _PAGE_RW|_PAGE_USER|_PAGE_HWWRITE
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@ -420,14 +446,12 @@ interrupt_base:
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/* Update 'changed'. */
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ori r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
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stw r11, 0(r12) /* Update Linux page table */
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stw r11, PTE_FLAGS_OFFSET(r12) /* Update Linux page table */
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/* MAS2 not updated as the entry does exist in the tlb, this
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fault taken to detect state transition (eg: COW -> DIRTY)
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*/
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lis r12, MAS3_RPN@h
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ori r12, r12, _PAGE_HWEXEC | MAS3_RPN@l
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and r11, r11, r12
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andi. r11, r11, _PAGE_HWEXEC
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rlwimi r11, r11, 31, 27, 27 /* SX <- _PAGE_HWEXEC */
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ori r11, r11, (MAS3_UW|MAS3_SW|MAS3_UR|MAS3_SR)@l /* set static perms */
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@ -439,7 +463,10 @@ interrupt_base:
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/* find the TLB index that caused the fault. It has to be here. */
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tlbsx 0, r10
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mtspr SPRN_MAS3,r11
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/* only update the perm bits, assume the RPN is fine */
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mfspr r12, SPRN_MAS3
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rlwimi r12, r11, 0, 20, 31
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mtspr SPRN_MAS3,r12
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tlbwe
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/* Done...restore registers and get out of here. */
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@ -530,18 +557,15 @@ interrupt_base:
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lwz r11,PGDIR(r11)
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4:
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rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
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lwz r11, 0(r11) /* Get L1 entry */
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rlwinm. r12, r11, 0, 0, 19 /* Extract L2 (pte) base address */
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beq 2f /* Bail if no table */
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rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
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lwz r11, 0(r12) /* Get Linux PTE */
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andi. r13, r11, _PAGE_PRESENT
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beq 2f
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FIND_PTE
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andi. r13, r11, _PAGE_PRESENT /* Is the page present? */
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beq 2f /* Bail if not present */
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#ifdef CONFIG_PTE_64BIT
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lwz r13, 0(r12)
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#endif
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ori r11, r11, _PAGE_ACCESSED
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stw r11, 0(r12)
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stw r11, PTE_FLAGS_OFFSET(r12)
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/* Jump to common tlb load */
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b finish_tlb_load
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@ -594,18 +618,15 @@ interrupt_base:
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lwz r11,PGDIR(r11)
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4:
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rlwimi r11, r10, 12, 20, 29 /* Create L1 (pgdir/pmd) address */
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lwz r11, 0(r11) /* Get L1 entry */
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rlwinm. r12, r11, 0, 0, 19 /* Extract L2 (pte) base address */
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beq 2f /* Bail if no table */
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rlwimi r12, r10, 22, 20, 29 /* Compute PTE address */
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lwz r11, 0(r12) /* Get Linux PTE */
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andi. r13, r11, _PAGE_PRESENT
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beq 2f
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FIND_PTE
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andi. r13, r11, _PAGE_PRESENT /* Is the page present? */
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beq 2f /* Bail if not present */
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#ifdef CONFIG_PTE_64BIT
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lwz r13, 0(r12)
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#endif
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ori r11, r11, _PAGE_ACCESSED
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stw r11, 0(r12)
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stw r11, PTE_FLAGS_OFFSET(r12)
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/* Jump to common TLB load point */
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b finish_tlb_load
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@ -690,27 +711,39 @@ finish_tlb_load:
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*/
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mfspr r12, SPRN_MAS2
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#ifdef CONFIG_PTE_64BIT
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rlwimi r12, r11, 26, 24, 31 /* extract ...WIMGE from pte */
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#else
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rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
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#endif
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mtspr SPRN_MAS2, r12
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bge 5, 1f
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/* addr > TASK_SIZE */
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li r10, (MAS3_UX | MAS3_UW | MAS3_UR)
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andi. r13, r11, (_PAGE_USER | _PAGE_HWWRITE | _PAGE_HWEXEC)
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andi. r12, r11, _PAGE_USER /* Test for _PAGE_USER */
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iseleq r12, 0, r10
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and r10, r12, r13
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srwi r12, r10, 1
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/* is user addr */
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andi. r12, r11, (_PAGE_USER | _PAGE_HWWRITE | _PAGE_HWEXEC)
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andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */
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srwi r10, r12, 1
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or r12, r12, r10 /* Copy user perms into supervisor */
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iseleq r12, 0, r12
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b 2f
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/* addr <= TASK_SIZE */
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/* is kernel addr */
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1: rlwinm r12, r11, 31, 29, 29 /* Extract _PAGE_HWWRITE into SW */
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ori r12, r12, (MAS3_SX | MAS3_SR)
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#ifdef CONFIG_PTE_64BIT
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2: rlwimi r12, r13, 24, 0, 7 /* grab RPN[32:39] */
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rlwimi r12, r11, 24, 8, 19 /* grab RPN[40:51] */
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mtspr SPRN_MAS3, r12
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BEGIN_FTR_SECTION
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srwi r10, r13, 8 /* grab RPN[8:31] */
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mtspr SPRN_MAS7, r10
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END_FTR_SECTION_IFSET(CPU_FTR_BIG_PHYS)
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#else
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2: rlwimi r11, r12, 0, 20, 31 /* Extract RPN from PTE and merge with perms */
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mtspr SPRN_MAS3, r11
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#endif
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tlbwe
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/* Done...restore registers and get out of here. */
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@ -31,3 +31,11 @@ get_ccsrbar(void)
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}
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EXPORT_SYMBOL(get_ccsrbar);
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/* For now this is a pass through */
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phys_addr_t fixup_bigphys_addr(phys_addr_t addr, phys_addr_t size)
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{
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return addr;
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};
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EXPORT_SYMBOL(fixup_bigphys_addr);
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@ -88,6 +88,7 @@ static inline unsigned int cpu_has_feature(unsigned int feature)
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#define CPU_FTR_HAS_HIGH_BATS 0x00010000
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#define CPU_FTR_NEED_COHERENT 0x00020000
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#define CPU_FTR_NO_BTIC 0x00040000
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#define CPU_FTR_BIG_PHYS 0x00080000
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#ifdef __ASSEMBLY__
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@ -225,8 +225,7 @@ extern unsigned long ioremap_bot, ioremap_base;
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/* ERPN in a PTE never gets cleared, ignore it */
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#define _PTE_NONE_MASK 0xffffffff00000000ULL
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#elif defined(CONFIG_E500)
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#elif defined(CONFIG_FSL_BOOKE)
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/*
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MMU Assist Register 3:
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@ -240,21 +239,29 @@ extern unsigned long ioremap_bot, ioremap_base;
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entries use the top 29 bits.
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*/
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/* Definitions for e500 core */
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#define _PAGE_PRESENT 0x001 /* S: PTE contains a translation */
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#define _PAGE_USER 0x002 /* S: User page (maps to UR) */
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#define _PAGE_FILE 0x002 /* S: when !present: nonlinear file mapping */
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#define _PAGE_ACCESSED 0x004 /* S: Page referenced */
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#define _PAGE_HWWRITE 0x008 /* H: Dirty & RW, set in exception */
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#define _PAGE_RW 0x010 /* S: Write permission */
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#define _PAGE_HWEXEC 0x020 /* H: UX permission */
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/* Definitions for FSL Book-E Cores */
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#define _PAGE_PRESENT 0x00001 /* S: PTE contains a translation */
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#define _PAGE_USER 0x00002 /* S: User page (maps to UR) */
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#define _PAGE_FILE 0x00002 /* S: when !present: nonlinear file mapping */
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#define _PAGE_ACCESSED 0x00004 /* S: Page referenced */
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#define _PAGE_HWWRITE 0x00008 /* H: Dirty & RW, set in exception */
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#define _PAGE_RW 0x00010 /* S: Write permission */
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#define _PAGE_HWEXEC 0x00020 /* H: UX permission */
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#define _PAGE_ENDIAN 0x040 /* H: E bit */
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#define _PAGE_GUARDED 0x080 /* H: G bit */
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#define _PAGE_COHERENT 0x100 /* H: M bit */
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#define _PAGE_NO_CACHE 0x200 /* H: I bit */
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#define _PAGE_WRITETHRU 0x400 /* H: W bit */
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#define _PAGE_DIRTY 0x800 /* S: Page dirty */
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#define _PAGE_ENDIAN 0x00040 /* H: E bit */
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#define _PAGE_GUARDED 0x00080 /* H: G bit */
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#define _PAGE_COHERENT 0x00100 /* H: M bit */
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#define _PAGE_NO_CACHE 0x00200 /* H: I bit */
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#define _PAGE_WRITETHRU 0x00400 /* H: W bit */
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#ifdef CONFIG_PTE_64BIT
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#define _PAGE_DIRTY 0x08000 /* S: Page dirty */
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/* ERPN in a PTE never gets cleared, ignore it */
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#define _PTE_NONE_MASK 0xffffffffffff0000ULL
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#else
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#define _PAGE_DIRTY 0x00800 /* S: Page dirty */
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#endif
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#define _PMD_PRESENT 0
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#define _PMD_PRESENT_MASK (PAGE_MASK)
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@ -433,7 +440,11 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
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/* in some case we want to additionaly adjust where the pfn is in the pte to
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* allow room for more flags */
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#if defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
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#define PFN_SHIFT_OFFSET (PAGE_SHIFT + 8)
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#else
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#define PFN_SHIFT_OFFSET (PAGE_SHIFT)
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#endif
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#define pte_pfn(x) (pte_val(x) >> PFN_SHIFT_OFFSET)
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#define pte_page(x) pfn_to_page(pte_pfn(x))
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@ -172,6 +172,7 @@ do { \
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#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
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#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
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#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
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#define SPRN_MAS7 0x3b0 /* MMU Assist Register 7 */
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#define SPRN_PID1 0x279 /* Process ID Register 1 */
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#define SPRN_PID2 0x27A /* Process ID Register 2 */
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#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
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