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staging: comedi: pcmuio: tidy up the register map defines
Add namespace to the register map defines. Gather them together and tidy them up a bit. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten
Greg Kroah-Hartman
parent
75ec11370e
commit
f45a1f26ea
@ -80,6 +80,34 @@
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#include "comedi_fc.h"
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/*
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* Register I/O map
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*
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* Offset Page 0 Page 1 Page 2 Page 3
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* ------ ----------- ----------- ----------- -----------
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* 0x00 Port 0 I/O Port 0 I/O Port 0 I/O Port 0 I/O
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* 0x01 Port 1 I/O Port 1 I/O Port 1 I/O Port 1 I/O
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* 0x02 Port 2 I/O Port 2 I/O Port 2 I/O Port 2 I/O
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* 0x03 Port 3 I/O Port 3 I/O Port 3 I/O Port 3 I/O
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* 0x04 Port 4 I/O Port 4 I/O Port 4 I/O Port 4 I/O
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* 0x05 Port 5 I/O Port 5 I/O Port 5 I/O Port 5 I/O
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* 0x06 INT_PENDING INT_PENDING INT_PENDING INT_PENDING
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* 0x07 Page/Lock Page/Lock Page/Lock Page/Lock
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* 0x08 N/A POL_0 ENAB_0 INT_ID0
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* 0x09 N/A POL_1 ENAB_1 INT_ID1
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* 0x0a N/A POL_2 ENAB_2 INT_ID2
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*/
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#define PCMUIO_PORT_REG(x) (0x00 + (x))
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#define PCMUIO_INT_PENDING_REG 0x06
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#define PCMUIO_PAGE_LOCK_REG 0x07
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#define PCMUIO_LOCK_PORT(x) ((1 << (x)) & 0x3f)
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#define PCMUIO_PAGE(x) (((x) & 0x3) << 6)
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#define PCMUIO_PAGE_MASK PCMUIO_PAGE(3)
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#define PCMUIO_PAGE_POL 1
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#define PCMUIO_PAGE_ENAB 2
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#define PCMUIO_PAGE_INT_ID 3
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#define PCMUIO_PAGE_REG(x) (0x08 + (x))
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#define CHANS_PER_PORT 8
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#define PORTS_PER_ASIC 6
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#define INTR_PORTS_PER_ASIC 3
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@ -97,53 +125,9 @@
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#define PCMUIO48_IOSIZE ASIC_IOSIZE
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#define PCMUIO96_IOSIZE (ASIC_IOSIZE * 2)
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/*
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* Some offsets - these are all in the 16byte IO memory offset from
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* the base address. Note that there is a paging scheme to swap out
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* offsets 0x8-0xA using the PAGELOCK register. See the table below.
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*
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* Register(s) Pages R/W? Description
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* --------------------------------------------------------------------------
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* REG_PORTx All R/W Read/Write/Configure IO
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* REG_INT_PENDING All ReadOnly Which INT_IDx has int.
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* REG_PAGELOCK All WriteOnly Select a page
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* REG_POLx Pg. 1 only WriteOnly Select edge-detection polarity
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* REG_ENABx Pg. 2 only WriteOnly Enable/Disable edge-detect int.
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* REG_INT_IDx Pg. 3 only R/W See which ports/bits have ints.
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*/
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#define REG_PORT0 0x0
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#define REG_PORT1 0x1
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#define REG_PORT2 0x2
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#define REG_PORT3 0x3
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#define REG_PORT4 0x4
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#define REG_PORT5 0x5
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#define REG_INT_PENDING 0x6
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/*
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* page selector register
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* Upper 2 bits select a page and bits 0-5 are used to
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* 'lock down' a particular port above to make it readonly.
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*/
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#define REG_PAGELOCK 0x7
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#define REG_POL0 0x8
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#define REG_POL1 0x9
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#define REG_POL2 0xa
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#define REG_ENAB0 0x8
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#define REG_ENAB1 0x9
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#define REG_ENAB2 0xa
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#define REG_INT_ID0 0x8
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#define REG_INT_ID1 0x9
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#define REG_INT_ID2 0xa
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#define NUM_PAGED_REGS 3
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#define NUM_PAGES 4
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#define FIRST_PAGED_REG 0x8
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#define REG_PAGE_BITOFFSET 6
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#define REG_LOCK_BITOFFSET 0
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#define REG_PAGE_MASK (~((0x1 << REG_PAGE_BITOFFSET) - 1))
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#define REG_LOCK_MASK ~(REG_PAGE_MASK)
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#define PAGE_POL 1
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#define PAGE_ENAB 2
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#define PAGE_INT_ID 3
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struct pcmuio_board {
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const char *name;
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@ -336,12 +320,12 @@ static void switch_page(struct comedi_device *dev, int asic, int page)
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if (page < 0 || page >= NUM_PAGES)
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return; /* more paranoia */
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devpriv->asics[asic].pagelock &= ~REG_PAGE_MASK;
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devpriv->asics[asic].pagelock |= page << REG_PAGE_BITOFFSET;
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devpriv->asics[asic].pagelock &= ~PCMUIO_PAGE_MASK;
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devpriv->asics[asic].pagelock |= PCMUIO_PAGE(page);
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/* now write out the shadow register */
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outb(devpriv->asics[asic].pagelock,
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dev->iobase + ASIC_IOSIZE * asic + REG_PAGELOCK);
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dev->iobase + ASIC_IOSIZE * asic + PCMUIO_PAGE_LOCK_REG);
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}
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static void init_asics(struct comedi_device *dev)
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@ -358,7 +342,7 @@ static void init_asics(struct comedi_device *dev)
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/* first, clear all the DIO port bits */
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for (port = 0; port < PORTS_PER_ASIC; ++port)
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outb(0, baseaddr + REG_PORT0 + port);
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outb(0, baseaddr + PCMUIO_PORT_REG(port));
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/* Next, clear all the paged registers for each page */
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for (page = 1; page < NUM_PAGES; ++page) {
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@ -370,13 +354,6 @@ static void init_asics(struct comedi_device *dev)
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outb(0, baseaddr + reg);
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}
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/* DEBUG set rising edge interrupts on port0 of both asics */
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/*switch_page(dev, asic, PAGE_POL);
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outb(0xff, baseaddr + REG_POL0);
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switch_page(dev, asic, PAGE_ENAB);
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outb(0xff, baseaddr + REG_ENAB0); */
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/* END DEBUG */
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/* switch back to default page 0 */
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switch_page(dev, asic, 0);
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}
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@ -398,10 +375,10 @@ static void pcmuio_stop_intr(struct comedi_device *dev,
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s->async->inttrig = NULL;
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nports = subpriv->intr.num_asic_chans / CHANS_PER_PORT;
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firstport = subpriv->intr.asic_chan / CHANS_PER_PORT;
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switch_page(dev, asic, PAGE_ENAB);
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switch_page(dev, asic, PCMUIO_PAGE_ENAB);
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for (port = firstport; port < firstport + nports; ++port) {
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/* disable all intrs for this subdev.. */
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outb(0, devpriv->asics[asic].iobase + REG_ENAB0 + port);
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outb(0, devpriv->asics[asic].iobase + PCMUIO_PAGE_REG(port));
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}
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}
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@ -478,17 +455,17 @@ static int pcmuio_handle_asic_interrupt(struct comedi_device *dev, int asic)
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spin_lock_irqsave(&devpriv->asics[asic].spinlock, flags);
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int_pend = inb(iobase + REG_INT_PENDING) & 0x07;
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int_pend = inb(iobase + PCMUIO_INT_PENDING_REG) & 0x07;
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if (int_pend) {
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for (i = 0; i < INTR_PORTS_PER_ASIC; ++i) {
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if (int_pend & (0x1 << i)) {
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unsigned char val;
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switch_page(dev, asic, PAGE_INT_ID);
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val = inb(iobase + REG_INT_ID0 + i);
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switch_page(dev, asic, PCMUIO_PAGE_INT_ID);
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val = inb(iobase + PCMUIO_PAGE_REG(i));
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if (val)
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/* clear pending interrupt */
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outb(0, iobase + REG_INT_ID0 + i);
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outb(0, iobase + PCMUIO_PAGE_REG(i));
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triggered |= (val << (i * 8));
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}
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@ -574,7 +551,7 @@ static int pcmuio_start_intr(struct comedi_device *dev,
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1) << subpriv->intr.first_chan;
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subpriv->intr.enabled_mask = bits;
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switch_page(dev, asic, PAGE_ENAB);
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switch_page(dev, asic, PCMUIO_PAGE_ENAB);
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for (port = firstport; port < firstport + nports; ++port) {
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unsigned enab =
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bits >> (subpriv->intr.first_chan + (port -
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@ -584,10 +561,10 @@ static int pcmuio_start_intr(struct comedi_device *dev,
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(port - firstport) * 8) & 0xff;
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/* set enab intrs for this subdev.. */
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outb(enab,
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devpriv->asics[asic].iobase + REG_ENAB0 + port);
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switch_page(dev, asic, PAGE_POL);
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devpriv->asics[asic].iobase + PCMUIO_PAGE_REG(port));
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switch_page(dev, asic, PCMUIO_PAGE_POL);
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outb(pol,
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devpriv->asics[asic].iobase + REG_ENAB0 + port);
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devpriv->asics[asic].iobase + PCMUIO_PAGE_REG(port));
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}
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}
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return 0;
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