mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 03:20:55 +07:00
powerpc/powernv: Split cxl code out into a separate file
The support for using the Mellanox CX4 in cxl mode will require additions to the PHB code. In preparation for this, move the existing cxl code out of pci-ioda.c into a separate pci-cxl.c file to keep things more organised. Signed-off-by: Ian Munsie <imunsie@au1.ibm.com> Reviewed-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com> Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Ian Munsie
Michael Ellerman
parent
fc9f75ef2f
commit
f456834a6c
@ -6,6 +6,7 @@ obj-y += opal-kmsg.o
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obj-$(CONFIG_SMP) += smp.o subcore.o subcore-asm.o
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obj-$(CONFIG_PCI) += pci.o pci-ioda.o npu-dma.o
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obj-$(CONFIG_CXL_BASE) += pci-cxl.o
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obj-$(CONFIG_EEH) += eeh-powernv.o
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obj-$(CONFIG_PPC_SCOM) += opal-xscom.o
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obj-$(CONFIG_MEMORY_FAILURE) += opal-memory-errors.o
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163
arch/powerpc/platforms/powernv/pci-cxl.c
Normal file
163
arch/powerpc/platforms/powernv/pci-cxl.c
Normal file
@ -0,0 +1,163 @@
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/*
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* Copyright 2014-2016 IBM Corp.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <asm/pnv-pci.h>
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#include <asm/opal.h>
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#include "pci.h"
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struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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return of_node_get(hose->dn);
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}
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EXPORT_SYMBOL(pnv_pci_get_phb_node);
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int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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struct pnv_ioda_pe *pe;
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int rc;
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pe = pnv_ioda_get_pe(dev);
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if (!pe)
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return -ENODEV;
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pe_info(pe, "Switching PHB to CXL\n");
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rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number);
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if (rc == OPAL_UNSUPPORTED)
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dev_err(&dev->dev, "Required cxl mode not supported by firmware - update skiboot\n");
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else if (rc)
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dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc);
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return rc;
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}
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EXPORT_SYMBOL(pnv_phb_to_cxl_mode);
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/* Find PHB for cxl dev and allocate MSI hwirqs?
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* Returns the absolute hardware IRQ number
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*/
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int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num);
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if (hwirq < 0) {
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dev_warn(&dev->dev, "Failed to find a free MSI\n");
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return -ENOSPC;
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}
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return phb->msi_base + hwirq;
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}
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EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs);
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void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num);
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}
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EXPORT_SYMBOL(pnv_cxl_release_hwirqs);
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void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs,
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struct pci_dev *dev)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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int i, hwirq;
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for (i = 1; i < CXL_IRQ_RANGES; i++) {
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if (!irqs->range[i])
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continue;
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pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n",
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i, irqs->offset[i],
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irqs->range[i]);
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hwirq = irqs->offset[i] - phb->msi_base;
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msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq,
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irqs->range[i]);
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}
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}
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EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges);
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int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs,
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struct pci_dev *dev, int num)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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int i, hwirq, try;
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memset(irqs, 0, sizeof(struct cxl_irq_ranges));
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/* 0 is reserved for the multiplexed PSL DSI interrupt */
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for (i = 1; i < CXL_IRQ_RANGES && num; i++) {
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try = num;
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while (try) {
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hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try);
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if (hwirq >= 0)
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break;
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try /= 2;
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}
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if (!try)
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goto fail;
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irqs->offset[i] = phb->msi_base + hwirq;
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irqs->range[i] = try;
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pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n",
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i, irqs->offset[i], irqs->range[i]);
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num -= try;
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}
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if (num)
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goto fail;
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return 0;
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fail:
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pnv_cxl_release_hwirq_ranges(irqs, dev);
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return -ENOSPC;
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}
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EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges);
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int pnv_cxl_get_irq_count(struct pci_dev *dev)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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return phb->msi_bmp.irq_count;
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}
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EXPORT_SYMBOL(pnv_cxl_get_irq_count);
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int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq,
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unsigned int virq)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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unsigned int xive_num = hwirq - phb->msi_base;
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struct pnv_ioda_pe *pe;
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int rc;
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if (!(pe = pnv_ioda_get_pe(dev)))
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return -ENODEV;
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/* Assign XIVE to PE */
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rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
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if (rc) {
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pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x "
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"hwirq 0x%x XIVE 0x%x PE\n",
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pci_name(dev), rc, phb->msi_base, hwirq, xive_num);
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return -EIO;
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}
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pnv_set_msi_irq_chip(phb, virq);
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return 0;
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}
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EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup);
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@ -595,7 +595,7 @@ static int pnv_ioda_get_pe_state(struct pnv_phb *phb, int pe_no)
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* but in the meantime, we need to protect them to avoid warnings
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*/
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#ifdef CONFIG_PCI_MSI
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static struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
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struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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@ -2700,7 +2700,7 @@ static void pnv_ioda2_msi_eoi(struct irq_data *d)
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}
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static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
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void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
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{
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struct irq_data *idata;
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struct irq_chip *ichip;
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@ -2722,159 +2722,6 @@ static void set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq)
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irq_set_chip(virq, &phb->ioda.irq_chip);
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}
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#ifdef CONFIG_CXL_BASE
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struct device_node *pnv_pci_get_phb_node(struct pci_dev *dev)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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return of_node_get(hose->dn);
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}
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EXPORT_SYMBOL(pnv_pci_get_phb_node);
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int pnv_phb_to_cxl_mode(struct pci_dev *dev, uint64_t mode)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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struct pnv_ioda_pe *pe;
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int rc;
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pe = pnv_ioda_get_pe(dev);
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if (!pe)
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return -ENODEV;
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pe_info(pe, "Switching PHB to CXL\n");
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rc = opal_pci_set_phb_cxl_mode(phb->opal_id, mode, pe->pe_number);
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if (rc == OPAL_UNSUPPORTED)
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dev_err(&dev->dev, "Required cxl mode not supported by firmware - update skiboot\n");
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else if (rc)
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dev_err(&dev->dev, "opal_pci_set_phb_cxl_mode failed: %i\n", rc);
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return rc;
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}
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EXPORT_SYMBOL(pnv_phb_to_cxl_mode);
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/* Find PHB for cxl dev and allocate MSI hwirqs?
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* Returns the absolute hardware IRQ number
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*/
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int pnv_cxl_alloc_hwirqs(struct pci_dev *dev, int num)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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int hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, num);
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if (hwirq < 0) {
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dev_warn(&dev->dev, "Failed to find a free MSI\n");
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return -ENOSPC;
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}
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return phb->msi_base + hwirq;
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}
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EXPORT_SYMBOL(pnv_cxl_alloc_hwirqs);
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void pnv_cxl_release_hwirqs(struct pci_dev *dev, int hwirq, int num)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq - phb->msi_base, num);
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}
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EXPORT_SYMBOL(pnv_cxl_release_hwirqs);
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void pnv_cxl_release_hwirq_ranges(struct cxl_irq_ranges *irqs,
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struct pci_dev *dev)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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int i, hwirq;
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for (i = 1; i < CXL_IRQ_RANGES; i++) {
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if (!irqs->range[i])
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continue;
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pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n",
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i, irqs->offset[i],
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irqs->range[i]);
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hwirq = irqs->offset[i] - phb->msi_base;
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msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq,
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irqs->range[i]);
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}
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}
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EXPORT_SYMBOL(pnv_cxl_release_hwirq_ranges);
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int pnv_cxl_alloc_hwirq_ranges(struct cxl_irq_ranges *irqs,
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struct pci_dev *dev, int num)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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int i, hwirq, try;
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memset(irqs, 0, sizeof(struct cxl_irq_ranges));
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/* 0 is reserved for the multiplexed PSL DSI interrupt */
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for (i = 1; i < CXL_IRQ_RANGES && num; i++) {
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try = num;
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while (try) {
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hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, try);
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if (hwirq >= 0)
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break;
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try /= 2;
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}
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if (!try)
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goto fail;
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irqs->offset[i] = phb->msi_base + hwirq;
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irqs->range[i] = try;
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pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n",
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i, irqs->offset[i], irqs->range[i]);
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num -= try;
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}
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if (num)
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goto fail;
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return 0;
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fail:
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pnv_cxl_release_hwirq_ranges(irqs, dev);
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return -ENOSPC;
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}
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EXPORT_SYMBOL(pnv_cxl_alloc_hwirq_ranges);
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int pnv_cxl_get_irq_count(struct pci_dev *dev)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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return phb->msi_bmp.irq_count;
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}
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EXPORT_SYMBOL(pnv_cxl_get_irq_count);
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int pnv_cxl_ioda_msi_setup(struct pci_dev *dev, unsigned int hwirq,
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unsigned int virq)
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{
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struct pci_controller *hose = pci_bus_to_host(dev->bus);
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struct pnv_phb *phb = hose->private_data;
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unsigned int xive_num = hwirq - phb->msi_base;
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struct pnv_ioda_pe *pe;
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int rc;
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if (!(pe = pnv_ioda_get_pe(dev)))
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return -ENODEV;
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/* Assign XIVE to PE */
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rc = opal_pci_set_xive_pe(phb->opal_id, pe->pe_number, xive_num);
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if (rc) {
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pe_warn(pe, "%s: OPAL error %d setting msi_base 0x%x "
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"hwirq 0x%x XIVE 0x%x PE\n",
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pci_name(dev), rc, phb->msi_base, hwirq, xive_num);
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return -EIO;
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}
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set_msi_irq_chip(phb, virq);
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return 0;
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}
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EXPORT_SYMBOL(pnv_cxl_ioda_msi_setup);
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#endif
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static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
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unsigned int hwirq, unsigned int virq,
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unsigned int is_64, struct msi_msg *msg)
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@ -2931,7 +2778,7 @@ static int pnv_pci_ioda_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
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}
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msg->data = be32_to_cpu(data);
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set_msi_irq_chip(phb, virq);
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pnv_set_msi_irq_chip(phb, virq);
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pr_devel("%s: %s-bit MSI on hwirq %x (xive #%d),"
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" address=%x_%08x data=%x PE# %d\n",
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@ -1,6 +1,10 @@
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#ifndef __POWERNV_PCI_H
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#define __POWERNV_PCI_H
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#include <linux/iommu.h>
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#include <asm/iommu.h>
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#include <asm/msi_bitmap.h>
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struct pci_dn;
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enum pnv_phb_type {
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@ -212,6 +216,8 @@ extern void pnv_pci_dma_dev_setup(struct pci_dev *pdev);
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extern void pnv_pci_dma_bus_setup(struct pci_bus *bus);
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extern int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
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extern void pnv_teardown_msi_irqs(struct pci_dev *pdev);
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extern struct pnv_ioda_pe *pnv_ioda_get_pe(struct pci_dev *dev);
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extern void pnv_set_msi_irq_chip(struct pnv_phb *phb, unsigned int virq);
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extern void pe_level_printk(const struct pnv_ioda_pe *pe, const char *level,
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const char *fmt, ...);
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