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dt-bindings: tegra: Remove 0, prefix from unit-addresses

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When Tegra124 support was first merged the unit-addresses of all devices
were listed with a "0," prefix to encode the reg property's second cell.
It turns out that this notation is not correct, and the "," separator is
only used to separate fields in the unit address (such as the device and
function number in PCI devices), not individual cells for addresses
with more than one cell.

Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Rob Herring <robh@kernel.org>
This commit is contained in:
Thierry Reding 2016-04-12 17:07:35 +02:00 committed by Rob Herring
parent 7aa5d38cfb
commit f43521e952
7 changed files with 12 additions and 12 deletions
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2
Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
View File

@ -50,7 +50,7 @@ Required properties for I2C mode:
Example:
clock@0,70110000 {
clock@70110000 {
compatible = "nvidia,tegra124-dfll";
reg = <0 0x70110000 0 0x100>, /* DFLL control */
<0 0x70110000 0 0x100>, /* I2C output control */

2
Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt
View File

@ -26,7 +26,7 @@ Required properties:
Example:
gpu@0,57000000 {
gpu@57000000 {
compatible = "nvidia,gk20a";
reg = <0x0 0x57000000 0x0 0x01000000>,
<0x0 0x58000000 0x0 0x01000000>;

6
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra-mc.txt
View File

@ -61,7 +61,7 @@ specified, according to the board documentation:
Example SoC include file:
/ {
mc: memory-controller@0,70019000 {
mc: memory-controller@70019000 {
compatible = "nvidia,tegra124-mc";
reg = <0x0 0x70019000 0x0 0x1000>;
clocks = <&tegra_car TEGRA124_CLK_MC>;
@ -72,7 +72,7 @@ Example SoC include file:
#iommu-cells = <1>;
};
sdhci@0,700b0000 {
sdhci@700b0000 {
compatible = "nvidia,tegra124-sdhci";
...
iommus = <&mc TEGRA_SWGROUP_SDMMC1A>;
@ -82,7 +82,7 @@ Example SoC include file:
Example board file:
/ {
memory-controller@0,70019000 {
memory-controller@70019000 {
emc-timings-3 {
nvidia,ram-code = <3>;

4
Documentation/devicetree/bindings/memory-controllers/tegra-emc.txt
View File

@ -190,7 +190,7 @@ be specified, according to the board documentation:
Example SoC include file:
/ {
emc@0,7001b000 {
emc@7001b000 {
compatible = "nvidia,tegra124-emc";
reg = <0x0 0x7001b000 0x0 0x1000>;
@ -201,7 +201,7 @@ Example SoC include file:
Example board file:
/ {
emc@0,7001b000 {
emc@7001b000 {
emc-timings-3 {
nvidia,ram-code = <3>;

6
Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-xusb-padctl.txt
View File

@ -79,7 +79,7 @@ Example:
SoC file extract:
-----------------
padctl@0,7009f000 {
padctl@7009f000 {
compatible = "nvidia,tegra124-xusb-padctl";
reg = <0x0 0x7009f000 0x0 0x1000>;
resets = <&tegra_car 142>;
@ -91,7 +91,7 @@ SoC file extract:
Board file extract:
-------------------
pcie-controller@0,01003000 {
pcie-controller@01003000 {
...
phys = <&padctl 0>;
@ -102,7 +102,7 @@ Board file extract:
...
padctl: padctl@0,7009f000 {
padctl: padctl@7009f000 {
pinctrl-0 = <&padctl_default>;
pinctrl-names = "default";

2
Documentation/devicetree/bindings/sound/nvidia,tegra30-hda.txt
View File

@ -15,7 +15,7 @@ Required properties:
Example:
hda@0,70030000 {
hda@70030000 {
compatible = "nvidia,tegra124-hda", "nvidia,tegra30-hda";
reg = <0x0 0x70030000 0x0 0x10000>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;

2
Documentation/devicetree/bindings/thermal/tegra-soctherm.txt
View File

@ -29,7 +29,7 @@ Required properties :
Example :
soctherm@0,700e2000 {
soctherm@700e2000 {
compatible = "nvidia,tegra124-soctherm";
reg = <0x0 0x700e2000 0x0 0x1000>;
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;