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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-02 16:46:41 +07:00
drm/radeon/kms: DCE6 disp eng pll updates
Rename the function to better match the functionality. DCPLL became PLL0 on DCE6. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -737,7 +737,7 @@ union set_pixel_clock {
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/* on DCE5, make sure the voltage is high enough to support the
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* required disp clk.
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*/
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static void atombios_crtc_set_dcpll(struct radeon_device *rdev,
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static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
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u32 dispclk)
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{
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u8 frev, crev;
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@ -767,7 +767,10 @@ static void atombios_crtc_set_dcpll(struct radeon_device *rdev,
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* SetPixelClock provides the dividers
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*/
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args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
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args.v6.ucPpll = ATOM_DCPLL;
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if (ASIC_IS_DCE6(rdev))
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args.v6.ucPpll = ATOM_PPLL0;
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else
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args.v6.ucPpll = ATOM_DCPLL;
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break;
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default:
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DRM_ERROR("Unknown table version %d %d\n", frev, crev);
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@ -1521,10 +1524,12 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
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}
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void radeon_atom_dcpll_init(struct radeon_device *rdev)
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void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
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{
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/* always set DCPLL */
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if (ASIC_IS_DCE4(rdev)) {
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if (ASIC_IS_DCE6(rdev))
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atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
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else if (ASIC_IS_DCE4(rdev)) {
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struct radeon_atom_ss ss;
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bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
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ASIC_INTERNAL_SS_ON_DCPLL,
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@ -1532,7 +1537,7 @@ void radeon_atom_dcpll_init(struct radeon_device *rdev)
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if (ss_enabled)
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atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, &ss);
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/* XXX: DCE5, make sure voltage, dispclk is high enough */
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atombios_crtc_set_dcpll(rdev, rdev->clock.default_dispclk);
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atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
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if (ss_enabled)
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atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, &ss);
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}
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@ -967,7 +967,7 @@ int radeon_resume_kms(struct drm_device *dev)
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/* init dig PHYs, disp eng pll */
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if (rdev->is_atom_bios) {
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radeon_atom_encoder_init(rdev);
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radeon_atom_dcpll_init(rdev);
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radeon_atom_disp_eng_pll_init(rdev);
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}
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/* reset hpd state */
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radeon_hpd_init(rdev);
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@ -1296,7 +1296,7 @@ int radeon_modeset_init(struct radeon_device *rdev)
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/* init dig PHYs, disp eng pll */
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if (rdev->is_atom_bios) {
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radeon_atom_encoder_init(rdev);
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radeon_atom_dcpll_init(rdev);
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radeon_atom_disp_eng_pll_init(rdev);
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}
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/* initialize hpd */
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@ -491,7 +491,7 @@ extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
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struct drm_connector *connector);
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extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
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extern void radeon_atom_encoder_init(struct radeon_device *rdev);
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extern void radeon_atom_dcpll_init(struct radeon_device *rdev);
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extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
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extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
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int action, uint8_t lane_num,
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uint8_t lane_set);
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