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x86, mce: fix reporting of Thermal Monitoring mechanism enabled
Early Pentium M models use different method for enabling TM2 (per paragraph 13.5.2.3 of the "Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A: System Programming Guide, Part 1"). Tested on the affected Pentium M variant (model == 13). Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> Cc: Andi Kleen <andi@firstfloor.org> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
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@ -222,6 +222,10 @@
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#define THERM_STATUS_PROCHOT (1 << 0)
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#define MSR_THERM2_CTL 0x0000019d
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#define MSR_THERM2_CTL_TM_SELECT (1ULL << 16)
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#define MSR_IA32_MISC_ENABLE 0x000001a0
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/* MISC_ENABLE bits: architectural */
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@ -253,9 +253,6 @@ void intel_init_thermal(struct cpuinfo_x86 *c)
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return;
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}
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if (cpu_has(c, X86_FEATURE_TM2) && (l & MSR_IA32_MISC_ENABLE_TM2))
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tm2 = 1;
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/* Check whether a vector already exists */
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if (h & APIC_VECTOR_MASK) {
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printk(KERN_DEBUG
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@ -264,6 +261,16 @@ void intel_init_thermal(struct cpuinfo_x86 *c)
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return;
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}
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/* early Pentium M models use different method for enabling TM2 */
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if (cpu_has(c, X86_FEATURE_TM2)) {
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if (c->x86 == 6 && (c->x86_model == 9 || c->x86_model == 13)) {
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rdmsr(MSR_THERM2_CTL, l, h);
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if (l & MSR_THERM2_CTL_TM_SELECT)
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tm2 = 1;
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} else if (l & MSR_IA32_MISC_ENABLE_TM2)
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tm2 = 1;
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}
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/* We'll mask the thermal vector in the lapic till we're ready: */
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h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED;
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apic_write(APIC_LVTTHMR, h);
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