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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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forcedeth: sideband management fix
This patch contains a fix that implements proper communication with the sideband management unit. Also, it makes sure that the speed is correctly set for gigabit phys in the case where sideband mgmt unit initialized the phy. Refer to bug #7684 for more details. Signed-Off-By: Ayaz Abdulla <aabdulla@nvidia.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
Ayaz Abdulla
Jeff Garzik
parent
e6331173c8
commit
f35723ec48
@ -234,6 +234,7 @@ enum {
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#define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
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#define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
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#define NVREG_XMITCTL_HOST_LOADED 0x00004000
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#define NVREG_XMITCTL_TX_PATH_EN 0x01000000
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NvRegTransmitterStatus = 0x088,
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#define NVREG_XMITSTAT_BUSY 0x01
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@ -249,6 +250,7 @@ enum {
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#define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
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NvRegReceiverControl = 0x094,
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#define NVREG_RCVCTL_START 0x01
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#define NVREG_RCVCTL_RX_PATH_EN 0x01000000
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NvRegReceiverStatus = 0x98,
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#define NVREG_RCVSTAT_BUSY 0x01
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@ -1169,16 +1171,21 @@ static void nv_start_rx(struct net_device *dev)
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{
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struct fe_priv *np = netdev_priv(dev);
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u8 __iomem *base = get_hwbase(dev);
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u32 rx_ctrl = readl(base + NvRegReceiverControl);
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dprintk(KERN_DEBUG "%s: nv_start_rx\n", dev->name);
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/* Already running? Stop it. */
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if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
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writel(0, base + NvRegReceiverControl);
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if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
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rx_ctrl &= ~NVREG_RCVCTL_START;
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writel(rx_ctrl, base + NvRegReceiverControl);
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pci_push(base);
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}
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writel(np->linkspeed, base + NvRegLinkSpeed);
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pci_push(base);
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writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
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rx_ctrl |= NVREG_RCVCTL_START;
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if (np->mac_in_use)
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rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
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writel(rx_ctrl, base + NvRegReceiverControl);
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dprintk(KERN_DEBUG "%s: nv_start_rx to duplex %d, speed 0x%08x.\n",
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dev->name, np->duplex, np->linkspeed);
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pci_push(base);
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@ -1186,39 +1193,59 @@ static void nv_start_rx(struct net_device *dev)
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static void nv_stop_rx(struct net_device *dev)
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{
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struct fe_priv *np = netdev_priv(dev);
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u8 __iomem *base = get_hwbase(dev);
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u32 rx_ctrl = readl(base + NvRegReceiverControl);
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dprintk(KERN_DEBUG "%s: nv_stop_rx\n", dev->name);
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writel(0, base + NvRegReceiverControl);
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if (!np->mac_in_use)
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rx_ctrl &= ~NVREG_RCVCTL_START;
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else
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rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
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writel(rx_ctrl, base + NvRegReceiverControl);
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reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
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NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
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KERN_INFO "nv_stop_rx: ReceiverStatus remained busy");
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udelay(NV_RXSTOP_DELAY2);
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writel(0, base + NvRegLinkSpeed);
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if (!np->mac_in_use)
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writel(0, base + NvRegLinkSpeed);
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}
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static void nv_start_tx(struct net_device *dev)
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{
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struct fe_priv *np = netdev_priv(dev);
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u8 __iomem *base = get_hwbase(dev);
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u32 tx_ctrl = readl(base + NvRegTransmitterControl);
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dprintk(KERN_DEBUG "%s: nv_start_tx\n", dev->name);
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writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
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tx_ctrl |= NVREG_XMITCTL_START;
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if (np->mac_in_use)
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tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
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writel(tx_ctrl, base + NvRegTransmitterControl);
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pci_push(base);
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}
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static void nv_stop_tx(struct net_device *dev)
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{
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struct fe_priv *np = netdev_priv(dev);
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u8 __iomem *base = get_hwbase(dev);
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u32 tx_ctrl = readl(base + NvRegTransmitterControl);
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dprintk(KERN_DEBUG "%s: nv_stop_tx\n", dev->name);
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writel(0, base + NvRegTransmitterControl);
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if (!np->mac_in_use)
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tx_ctrl &= ~NVREG_XMITCTL_START;
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else
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tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
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writel(tx_ctrl, base + NvRegTransmitterControl);
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reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
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NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
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KERN_INFO "nv_stop_tx: TransmitterStatus remained busy");
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udelay(NV_TXSTOP_DELAY2);
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writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
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if (!np->mac_in_use)
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writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
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base + NvRegTransmitPoll);
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}
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static void nv_txrx_reset(struct net_device *dev)
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@ -4148,20 +4175,6 @@ static int nv_mgmt_acquire_sema(struct net_device *dev)
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return 0;
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}
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/* Indicate to mgmt unit whether driver is loaded or not */
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static void nv_mgmt_driver_loaded(struct net_device *dev, int loaded)
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{
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u8 __iomem *base = get_hwbase(dev);
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u32 tx_ctrl;
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tx_ctrl = readl(base + NvRegTransmitterControl);
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if (loaded)
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tx_ctrl |= NVREG_XMITCTL_HOST_LOADED;
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else
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tx_ctrl &= ~NVREG_XMITCTL_HOST_LOADED;
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writel(tx_ctrl, base + NvRegTransmitterControl);
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}
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static int nv_open(struct net_device *dev)
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{
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struct fe_priv *np = netdev_priv(dev);
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@ -4659,33 +4672,24 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
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writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
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if (id->driver_data & DEV_HAS_MGMT_UNIT) {
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writel(0x1, base + 0x204); pci_push(base);
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msleep(500);
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/* management unit running on the mac? */
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np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST;
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if (np->mac_in_use) {
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u32 mgmt_sync;
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/* management unit setup the phy already? */
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mgmt_sync = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK;
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if (mgmt_sync == NVREG_XMITCTL_SYNC_NOT_READY) {
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if (!nv_mgmt_acquire_sema(dev)) {
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for (i = 0; i < 5000; i++) {
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msleep(1);
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mgmt_sync = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK;
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if (mgmt_sync == NVREG_XMITCTL_SYNC_NOT_READY)
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continue;
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if (mgmt_sync == NVREG_XMITCTL_SYNC_PHY_INIT)
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phyinitialized = 1;
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break;
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if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) {
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np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST;
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dprintk(KERN_INFO "%s: mgmt unit is running. mac in use %x.\n", pci_name(pci_dev), np->mac_in_use);
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for (i = 0; i < 5000; i++) {
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msleep(1);
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if (nv_mgmt_acquire_sema(dev)) {
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/* management unit setup the phy already? */
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if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
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NVREG_XMITCTL_SYNC_PHY_INIT) {
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/* phy is inited by mgmt unit */
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phyinitialized = 1;
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dprintk(KERN_INFO "%s: Phy already initialized by mgmt unit.\n", pci_name(pci_dev));
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} else {
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/* we need to init the phy */
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}
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} else {
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/* we need to init the phy */
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break;
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}
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} else if (mgmt_sync == NVREG_XMITCTL_SYNC_PHY_INIT) {
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/* phy is inited by SMU */
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phyinitialized = 1;
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} else {
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/* we need to init the phy */
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}
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}
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}
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@ -4724,10 +4728,12 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
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if (!phyinitialized) {
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/* reset it */
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phy_init(dev);
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}
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if (id->driver_data & DEV_HAS_MGMT_UNIT) {
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nv_mgmt_driver_loaded(dev, 1);
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} else {
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/* see if it is a gigabit phy */
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u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
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if (mii_status & PHY_GIGABIT) {
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np->gigabit = PHY_GIGABIT;
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}
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}
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/* set default link speed settings */
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@ -4749,8 +4755,6 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
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out_error:
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if (phystate_orig)
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writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
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if (np->mac_in_use)
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nv_mgmt_driver_loaded(dev, 0);
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pci_set_drvdata(pci_dev, NULL);
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out_freering:
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free_rings(dev);
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@ -4780,9 +4784,6 @@ static void __devexit nv_remove(struct pci_dev *pci_dev)
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writel(np->orig_mac[0], base + NvRegMacAddrA);
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writel(np->orig_mac[1], base + NvRegMacAddrB);
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if (np->mac_in_use)
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nv_mgmt_driver_loaded(dev, 0);
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/* free all structures */
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free_rings(dev);
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iounmap(get_hwbase(dev));
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