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drm/amdgpu: move validation of the VM size into the VM code
This moves validation of the VM size parameter into amdgpu_vm_adjust_size(). Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1187,22 +1187,8 @@ static void amdgpu_check_vm_size(struct amdgpu_device *adev)
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if (amdgpu_vm_size < 1) {
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dev_warn(adev->dev, "VM size (%d) too small, min is 1GB\n",
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amdgpu_vm_size);
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goto def_value;
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amdgpu_vm_size = -1;
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}
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/*
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* Max GPUVM size for Cayman, SI, CI VI are 40 bits.
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*/
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if (amdgpu_vm_size > 1024) {
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dev_warn(adev->dev, "VM size (%d) too large, max is 1TB\n",
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amdgpu_vm_size);
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goto def_value;
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}
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return;
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def_value:
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amdgpu_vm_size = -1;
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}
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/**
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@ -2580,13 +2580,22 @@ static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
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* @vm_size: the default vm size if it's set auto
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*/
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void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
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uint32_t fragment_size_default, unsigned max_level)
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uint32_t fragment_size_default, unsigned max_level,
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unsigned max_bits)
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{
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uint64_t tmp;
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/* adjust vm size first */
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if (amdgpu_vm_size != -1)
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if (amdgpu_vm_size != -1) {
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unsigned max_size = 1 << (max_bits - 30);
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vm_size = amdgpu_vm_size;
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if (vm_size > max_size) {
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dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
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amdgpu_vm_size, max_size);
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vm_size = max_size;
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}
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}
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adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
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@ -325,7 +325,8 @@ struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
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void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
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struct amdgpu_bo_va *bo_va);
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void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
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uint32_t fragment_size_default, unsigned max_level);
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uint32_t fragment_size_default, unsigned max_level,
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unsigned max_bits);
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int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
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bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
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struct amdgpu_job *job);
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@ -832,7 +832,7 @@ static int gmc_v6_0_sw_init(void *handle)
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if (r)
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return r;
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amdgpu_vm_adjust_size(adev, 64, 9, 1);
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amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
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adev->mc.mc_mask = 0xffffffffffULL;
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@ -971,7 +971,7 @@ static int gmc_v7_0_sw_init(void *handle)
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* Currently set to 4GB ((1 << 20) 4k pages).
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* Max GPUVM size for cayman and SI is 40 bits.
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*/
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amdgpu_vm_adjust_size(adev, 64, 9, 1);
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amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
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/* Set the internal MC address mask
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* This is the max address of the GPU's
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@ -1068,7 +1068,7 @@ static int gmc_v8_0_sw_init(void *handle)
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* Currently set to 4GB ((1 << 20) 4k pages).
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* Max GPUVM size for cayman and SI is 40 bits.
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*/
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amdgpu_vm_adjust_size(adev, 64, 9, 1);
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amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
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/* Set the internal MC address mask
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* This is the max address of the GPU's
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@ -770,10 +770,10 @@ static int gmc_v9_0_sw_init(void *handle)
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case CHIP_RAVEN:
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adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
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if (adev->rev_id == 0x0 || adev->rev_id == 0x1)
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amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3);
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amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
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else
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/* vm_size is 64GB for legacy 2-level page support */
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amdgpu_vm_adjust_size(adev, 64, 9, 1);
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amdgpu_vm_adjust_size(adev, 64, 9, 1, 48);
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break;
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case CHIP_VEGA10:
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/* XXX Don't know how to get VRAM type yet. */
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@ -783,7 +783,7 @@ static int gmc_v9_0_sw_init(void *handle)
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* vm size is 256TB (48bit), maximum size of Vega10,
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* block size 512 (9bit)
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*/
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amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3);
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amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
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break;
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default:
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break;
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