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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 12:06:41 +07:00
x86/xor: Add alternative SSE implementation only prefetching once per 64-byte line
On CPUs with 64-byte last level cache lines, this yields roughly 10% better performance, independent of CPU vendor or specific model (as far as I was able to test). Signed-off-by: Jan Beulich <jbeulich@suse.com> Acked-by: H. Peter Anvin <hpa@zytor.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Link: http://lkml.kernel.org/r/5093E4B802000078000A615E@nat28.tlf.novell.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Jan Beulich
Ingo Molnar
parent
e8f6e3f8a1
commit
f317820cb6
@ -58,6 +58,14 @@
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#define XO2(x, y) " xorps "OFFS(x)"(%[p3]), %%xmm"#y" ;\n"
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#define XO3(x, y) " xorps "OFFS(x)"(%[p4]), %%xmm"#y" ;\n"
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#define XO4(x, y) " xorps "OFFS(x)"(%[p5]), %%xmm"#y" ;\n"
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#define NOP(x)
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#define BLK64(pf, op, i) \
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pf(i) \
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op(i, 0) \
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op(i + 1, 1) \
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op(i + 2, 2) \
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op(i + 3, 3)
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static void
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xor_sse_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
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@ -110,6 +118,40 @@ xor_sse_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
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kernel_fpu_end();
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}
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static void
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xor_sse_2_pf64(unsigned long bytes, unsigned long *p1, unsigned long *p2)
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{
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unsigned long lines = bytes >> 8;
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kernel_fpu_begin();
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asm volatile(
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#undef BLOCK
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#define BLOCK(i) \
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BLK64(PF0, LD, i) \
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BLK64(PF1, XO1, i) \
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BLK64(NOP, ST, i) \
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" .align 32 ;\n"
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" 1: ;\n"
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BLOCK(0)
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BLOCK(4)
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BLOCK(8)
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BLOCK(12)
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" add %[inc], %[p1] ;\n"
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" add %[inc], %[p2] ;\n"
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" dec %[cnt] ;\n"
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" jnz 1b ;\n"
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: [cnt] "+r" (lines),
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[p1] "+r" (p1), [p2] "+r" (p2)
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: [inc] XOR_CONSTANT_CONSTRAINT (256UL)
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: "memory");
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kernel_fpu_end();
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}
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static void
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xor_sse_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
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unsigned long *p3)
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@ -169,6 +211,43 @@ xor_sse_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
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kernel_fpu_end();
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}
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static void
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xor_sse_3_pf64(unsigned long bytes, unsigned long *p1, unsigned long *p2,
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unsigned long *p3)
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{
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unsigned long lines = bytes >> 8;
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kernel_fpu_begin();
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asm volatile(
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#undef BLOCK
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#define BLOCK(i) \
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BLK64(PF0, LD, i) \
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BLK64(PF1, XO1, i) \
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BLK64(PF2, XO2, i) \
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BLK64(NOP, ST, i) \
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" .align 32 ;\n"
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" 1: ;\n"
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BLOCK(0)
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BLOCK(4)
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BLOCK(8)
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BLOCK(12)
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" add %[inc], %[p1] ;\n"
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" add %[inc], %[p2] ;\n"
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" add %[inc], %[p3] ;\n"
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" dec %[cnt] ;\n"
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" jnz 1b ;\n"
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: [cnt] "+r" (lines),
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[p1] "+r" (p1), [p2] "+r" (p2), [p3] "+r" (p3)
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: [inc] XOR_CONSTANT_CONSTRAINT (256UL)
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: "memory");
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kernel_fpu_end();
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}
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static void
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xor_sse_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
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unsigned long *p3, unsigned long *p4)
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@ -235,6 +314,45 @@ xor_sse_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
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kernel_fpu_end();
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}
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static void
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xor_sse_4_pf64(unsigned long bytes, unsigned long *p1, unsigned long *p2,
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unsigned long *p3, unsigned long *p4)
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{
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unsigned long lines = bytes >> 8;
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kernel_fpu_begin();
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asm volatile(
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#undef BLOCK
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#define BLOCK(i) \
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BLK64(PF0, LD, i) \
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BLK64(PF1, XO1, i) \
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BLK64(PF2, XO2, i) \
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BLK64(PF3, XO3, i) \
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BLK64(NOP, ST, i) \
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" .align 32 ;\n"
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" 1: ;\n"
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BLOCK(0)
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BLOCK(4)
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BLOCK(8)
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BLOCK(12)
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" add %[inc], %[p1] ;\n"
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" add %[inc], %[p2] ;\n"
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" add %[inc], %[p3] ;\n"
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" add %[inc], %[p4] ;\n"
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" dec %[cnt] ;\n"
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" jnz 1b ;\n"
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: [cnt] "+r" (lines), [p1] "+r" (p1),
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[p2] "+r" (p2), [p3] "+r" (p3), [p4] "+r" (p4)
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: [inc] XOR_CONSTANT_CONSTRAINT (256UL)
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: "memory");
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kernel_fpu_end();
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}
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static void
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xor_sse_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
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unsigned long *p3, unsigned long *p4, unsigned long *p5)
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@ -308,12 +426,63 @@ xor_sse_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
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kernel_fpu_end();
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}
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static void
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xor_sse_5_pf64(unsigned long bytes, unsigned long *p1, unsigned long *p2,
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unsigned long *p3, unsigned long *p4, unsigned long *p5)
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{
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unsigned long lines = bytes >> 8;
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kernel_fpu_begin();
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asm volatile(
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#undef BLOCK
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#define BLOCK(i) \
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BLK64(PF0, LD, i) \
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BLK64(PF1, XO1, i) \
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BLK64(PF2, XO2, i) \
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BLK64(PF3, XO3, i) \
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BLK64(PF4, XO4, i) \
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BLK64(NOP, ST, i) \
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" .align 32 ;\n"
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" 1: ;\n"
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BLOCK(0)
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BLOCK(4)
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BLOCK(8)
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BLOCK(12)
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" add %[inc], %[p1] ;\n"
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" add %[inc], %[p2] ;\n"
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" add %[inc], %[p3] ;\n"
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" add %[inc], %[p4] ;\n"
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" add %[inc], %[p5] ;\n"
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" dec %[cnt] ;\n"
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" jnz 1b ;\n"
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: [cnt] "+r" (lines), [p1] "+r" (p1), [p2] "+r" (p2),
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[p3] "+r" (p3), [p4] "+r" (p4), [p5] "+r" (p5)
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: [inc] XOR_CONSTANT_CONSTRAINT (256UL)
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: "memory");
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kernel_fpu_end();
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}
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static struct xor_block_template xor_block_sse_pf64 = {
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.name = "prefetch64-sse",
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.do_2 = xor_sse_2_pf64,
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.do_3 = xor_sse_3_pf64,
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.do_4 = xor_sse_4_pf64,
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.do_5 = xor_sse_5_pf64,
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};
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#undef LD
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#undef XO1
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#undef XO2
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#undef XO3
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#undef XO4
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#undef ST
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#undef NOP
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#undef BLK64
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#undef BLOCK
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#undef XOR_CONSTANT_CONSTRAINT
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@ -324,4 +493,7 @@ xor_sse_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
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# include <asm/xor_64.h>
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#endif
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#define XOR_SELECT_TEMPLATE(FASTEST) \
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AVX_SELECT(FASTEST)
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#endif /* _ASM_X86_XOR_H */
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@ -543,26 +543,25 @@ static struct xor_block_template xor_block_pIII_sse = {
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/* Also try the generic routines. */
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#include <asm-generic/xor.h>
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#undef XOR_TRY_TEMPLATES
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#define XOR_TRY_TEMPLATES \
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do { \
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xor_speed(&xor_block_8regs); \
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xor_speed(&xor_block_8regs_p); \
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xor_speed(&xor_block_32regs); \
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xor_speed(&xor_block_32regs_p); \
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AVX_XOR_SPEED; \
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if (cpu_has_xmm) \
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xor_speed(&xor_block_pIII_sse); \
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if (cpu_has_mmx) { \
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xor_speed(&xor_block_pII_mmx); \
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xor_speed(&xor_block_p5_mmx); \
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} \
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} while (0)
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/* We force the use of the SSE xor block because it can write around L2.
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We may also be able to load into the L1 only depending on how the cpu
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deals with a load to a line that is being prefetched. */
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#define XOR_SELECT_TEMPLATE(FASTEST) \
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AVX_SELECT(cpu_has_xmm ? &xor_block_pIII_sse : FASTEST)
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#undef XOR_TRY_TEMPLATES
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#define XOR_TRY_TEMPLATES \
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do { \
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AVX_XOR_SPEED; \
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if (cpu_has_xmm) { \
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xor_speed(&xor_block_pIII_sse); \
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xor_speed(&xor_block_sse_pf64); \
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} else if (cpu_has_mmx) { \
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xor_speed(&xor_block_pII_mmx); \
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xor_speed(&xor_block_p5_mmx); \
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} else { \
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xor_speed(&xor_block_8regs); \
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xor_speed(&xor_block_8regs_p); \
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xor_speed(&xor_block_32regs); \
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xor_speed(&xor_block_32regs_p); \
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} \
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} while (0)
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#endif /* _ASM_X86_XOR_32_H */
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@ -13,17 +13,15 @@ static struct xor_block_template xor_block_sse = {
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/* Also try the AVX routines */
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#include <asm/xor_avx.h>
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/* We force the use of the SSE xor block because it can write around L2.
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We may also be able to load into the L1 only depending on how the cpu
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deals with a load to a line that is being prefetched. */
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#undef XOR_TRY_TEMPLATES
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#define XOR_TRY_TEMPLATES \
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do { \
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AVX_XOR_SPEED; \
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xor_speed(&xor_block_sse_pf64); \
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xor_speed(&xor_block_sse); \
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} while (0)
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/* We force the use of the SSE xor block because it can write around L2.
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We may also be able to load into the L1 only depending on how the cpu
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deals with a load to a line that is being prefetched. */
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#define XOR_SELECT_TEMPLATE(FASTEST) \
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AVX_SELECT(&xor_block_sse)
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#endif /* _ASM_X86_XOR_64_H */
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