mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-24 13:00:54 +07:00
sh: clkfwk: Build fix for non-legacy CPG changes.
The disabling of the init op for non-legacy clocks neglected to do the same in the core clock framework, resulting in a build failure. Fix it up. Reported-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
parent
549015c36b
commit
f278ea849e
@ -418,8 +418,11 @@ int clk_register(struct clk *clk)
|
||||
list_add(&clk->sibling, &root_clks);
|
||||
|
||||
list_add(&clk->node, &clock_list);
|
||||
|
||||
#ifdef CONFIG_SH_CLK_CPG_LEGACY
|
||||
if (clk->ops && clk->ops->init)
|
||||
clk->ops->init(clk);
|
||||
#endif
|
||||
|
||||
out_unlock:
|
||||
mutex_unlock(&clock_list_sem);
|
||||
|
@ -131,7 +131,7 @@ static int sh_clk_div6_enable(struct clk *clk)
|
||||
unsigned long value;
|
||||
int ret;
|
||||
|
||||
ret = sh_clk_div6_set_rate(clk, clk->rate, 0);
|
||||
ret = sh_clk_div6_set_rate(clk, clk->rate);
|
||||
if (ret == 0) {
|
||||
value = __raw_readl(clk->enable_reg);
|
||||
value &= ~0x100; /* clear stop bit to enable clock */
|
||||
|
Loading…
Reference in New Issue
Block a user