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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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MIPS: Rewrite sysmips(MIPS_ATOMIC_SET, ...) in C with inline assembler
This way it doesn't have to use CONFIG_CPU_HAS_LLSC anymore. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
parent
f4c6b6bc5a
commit
f1e39a4a61
@ -32,6 +32,9 @@ extern asmlinkage void *resume(void *last, void *next, void *next_ti);
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struct task_struct;
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extern unsigned int ll_bit;
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extern struct task_struct *ll_task;
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#ifdef CONFIG_MIPS_MT_FPAFF
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/*
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@ -187,78 +187,6 @@ illegal_syscall:
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j o32_syscall_exit
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END(handle_sys)
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LEAF(mips_atomic_set)
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andi v0, a1, 3 # must be word aligned
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bnez v0, bad_alignment
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lw v1, TI_ADDR_LIMIT($28) # in legal address range?
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addiu a0, a1, 4
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or a0, a0, a1
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and a0, a0, v1
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bltz a0, bad_address
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#ifdef CONFIG_CPU_HAS_LLSC
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/* Ok, this is the ll/sc case. World is sane :-) */
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1: ll v0, (a1)
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move a0, a2
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2: sc a0, (a1)
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#if R10000_LLSC_WAR
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beqzl a0, 1b
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#else
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beqz a0, 1b
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#endif
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.section __ex_table,"a"
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PTR 1b, bad_stack
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PTR 2b, bad_stack
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.previous
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#else
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sw a1, 16(sp)
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sw a2, 20(sp)
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move a0, sp
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move a2, a1
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li a1, 1
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jal do_page_fault
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lw a1, 16(sp)
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lw a2, 20(sp)
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/*
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* At this point the page should be readable and writable unless
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* there was no more memory available.
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*/
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1: lw v0, (a1)
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2: sw a2, (a1)
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.section __ex_table,"a"
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PTR 1b, no_mem
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PTR 2b, no_mem
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.previous
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#endif
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sw zero, PT_R7(sp) # success
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sw v0, PT_R2(sp) # result
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j o32_syscall_exit # continue like a normal syscall
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no_mem: li v0, -ENOMEM
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jr ra
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bad_address:
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li v0, -EFAULT
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jr ra
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bad_alignment:
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li v0, -EINVAL
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jr ra
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END(mips_atomic_set)
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LEAF(sys_sysmips)
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beq a0, MIPS_ATOMIC_SET, mips_atomic_set
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j _sys_sysmips
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END(sys_sysmips)
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LEAF(sys_syscall)
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subu t0, a0, __NR_O32_Linux # check syscall number
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sltiu v0, t0, __NR_O32_Linux_syscalls + 1
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@ -124,78 +124,6 @@ illegal_syscall:
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j n64_syscall_exit
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END(handle_sys64)
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LEAF(mips_atomic_set)
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andi v0, a1, 3 # must be word aligned
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bnez v0, bad_alignment
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LONG_L v1, TI_ADDR_LIMIT($28) # in legal address range?
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LONG_ADDIU a0, a1, 4
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or a0, a0, a1
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and a0, a0, v1
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bltz a0, bad_address
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#ifdef CONFIG_CPU_HAS_LLSC
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/* Ok, this is the ll/sc case. World is sane :-) */
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1: ll v0, (a1)
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move a0, a2
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2: sc a0, (a1)
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#if R10000_LLSC_WAR
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beqzl a0, 1b
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#else
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beqz a0, 1b
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#endif
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.section __ex_table,"a"
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PTR 1b, bad_stack
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PTR 2b, bad_stack
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.previous
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#else
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sw a1, 16(sp)
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sw a2, 20(sp)
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move a0, sp
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move a2, a1
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li a1, 1
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jal do_page_fault
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lw a1, 16(sp)
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lw a2, 20(sp)
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/*
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* At this point the page should be readable and writable unless
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* there was no more memory available.
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*/
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1: lw v0, (a1)
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2: sw a2, (a1)
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.section __ex_table,"a"
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PTR 1b, no_mem
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PTR 2b, no_mem
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.previous
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#endif
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sd zero, PT_R7(sp) # success
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sd v0, PT_R2(sp) # result
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j n64_syscall_exit # continue like a normal syscall
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no_mem: li v0, -ENOMEM
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jr ra
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bad_address:
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li v0, -EFAULT
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jr ra
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bad_alignment:
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li v0, -EINVAL
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jr ra
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END(mips_atomic_set)
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LEAF(sys_sysmips)
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beq a0, MIPS_ATOMIC_SET, mips_atomic_set
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j _sys_sysmips
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END(sys_sysmips)
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.align 3
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sys_call_table:
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PTR sys_read /* 5000 */
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@ -28,7 +28,9 @@
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#include <linux/compiler.h>
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#include <linux/module.h>
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#include <linux/ipc.h>
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#include <linux/uaccess.h>
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#include <asm/asm.h>
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#include <asm/branch.h>
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#include <asm/cachectl.h>
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#include <asm/cacheflush.h>
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@ -290,12 +292,116 @@ SYSCALL_DEFINE1(set_thread_area, unsigned long, addr)
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return 0;
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}
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asmlinkage int _sys_sysmips(long cmd, long arg1, long arg2, long arg3)
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static inline int mips_atomic_set(struct pt_regs *regs,
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unsigned long addr, unsigned long new)
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{
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unsigned long old, tmp;
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unsigned int err;
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if (unlikely(addr & 3))
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return -EINVAL;
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if (unlikely(!access_ok(VERIFY_WRITE, addr, 4)))
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return -EINVAL;
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if (cpu_has_llsc && R10000_LLSC_WAR) {
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__asm__ __volatile__ (
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" li %[err], 0 \n"
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"1: ll %[old], (%[addr]) \n"
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" move %[tmp], %[new] \n"
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"2: sc %[tmp], (%[addr]) \n"
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" beqzl %[tmp], 1b \n"
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"3: \n"
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" .section .fixup,\"ax\" \n"
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"4: li %[err], %[efault] \n"
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" j 3b \n"
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" .previous \n"
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" .section __ex_table,\"a\" \n"
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" "STR(PTR)" 1b, 4b \n"
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" "STR(PTR)" 2b, 4b \n"
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" .previous \n"
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: [old] "=&r" (old),
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[err] "=&r" (err),
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[tmp] "=&r" (tmp)
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: [addr] "r" (addr),
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[new] "r" (new),
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[efault] "i" (-EFAULT)
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: "memory");
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} else if (cpu_has_llsc) {
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__asm__ __volatile__ (
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" li %[err], 0 \n"
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"1: ll %[old], (%[addr]) \n"
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" move %[tmp], %[new] \n"
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"2: sc %[tmp], (%[addr]) \n"
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" bnez %[tmp], 4f \n"
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"3: \n"
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" .subsection 2 \n"
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"4: b 1b \n"
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" .previous \n"
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" \n"
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" .section .fixup,\"ax\" \n"
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"5: li %[err], %[efault] \n"
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" j 3b \n"
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" .previous \n"
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" .section __ex_table,\"a\" \n"
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" "STR(PTR)" 1b, 5b \n"
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" "STR(PTR)" 2b, 5b \n"
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" .previous \n"
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: [old] "=&r" (old),
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[err] "=&r" (err),
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[tmp] "=&r" (tmp)
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: [addr] "r" (addr),
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[new] "r" (new),
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[efault] "i" (-EFAULT)
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: "memory");
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} else {
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do {
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preempt_disable();
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ll_bit = 1;
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ll_task = current;
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preempt_enable();
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err = __get_user(old, (unsigned int *) addr);
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err |= __put_user(new, (unsigned int *) addr);
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if (err)
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break;
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rmb();
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} while (!ll_bit);
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}
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if (unlikely(err))
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return err;
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regs->regs[2] = old;
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regs->regs[7] = 0; /* No error */
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/*
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* Don't let your children do this ...
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*/
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__asm__ __volatile__(
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" move $29, %0 \n"
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" j syscall_exit \n"
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: /* no outputs */
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: "r" (regs));
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/* unreached. Honestly. */
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while (1);
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}
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save_static_function(sys_sysmips);
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static int __used noinline
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_sys_sysmips(nabi_no_regargs struct pt_regs regs)
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{
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long cmd, arg1, arg2, arg3;
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cmd = regs.regs[4];
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arg1 = regs.regs[5];
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arg2 = regs.regs[6];
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arg3 = regs.regs[7];
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switch (cmd) {
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case MIPS_ATOMIC_SET:
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printk(KERN_CRIT "How did I get here?\n");
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return -EINVAL;
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return mips_atomic_set(®s, arg1, arg2);
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case MIPS_FIXADE:
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if (arg1 & ~3)
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@ -466,9 +466,8 @@ asmlinkage void do_be(struct pt_regs *regs)
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* The ll_bit is cleared by r*_switch.S
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*/
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unsigned long ll_bit;
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static struct task_struct *ll_task = NULL;
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unsigned int ll_bit;
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struct task_struct *ll_task;
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static inline int simulate_ll(struct pt_regs *regs, unsigned int opcode)
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{
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