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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-03-10 18:10:47 +07:00
mtd: pxa3xx_nand: rework flash detection and timing setup
Rework the pxa3xx_nand driver to allow using functions exported by the nand framework to detect the flash and the timings. Then setup the timings using the helpers previously added. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This commit is contained in:
Antoine Ténart
Brian Norris
parent
3f225b7f52
commit
f19fe9833d
@ -1396,45 +1396,23 @@ static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
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return NAND_STATUS_READY;
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}
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static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
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const struct pxa3xx_nand_flash *f)
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static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info)
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{
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struct platform_device *pdev = info->pdev;
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struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
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struct pxa3xx_nand_host *host = info->host[info->cs];
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uint32_t ndcr = 0x0; /* enable all interrupts */
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struct mtd_info *mtd = host->mtd;
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struct nand_chip *chip = mtd->priv;
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if (f->page_size != 2048 && f->page_size != 512) {
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dev_err(&pdev->dev, "Current only support 2048 and 512 size\n");
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return -EINVAL;
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}
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/* configure default flash values */
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info->reg_ndcr = 0x0; /* enable all interrupts */
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info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
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info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
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info->reg_ndcr |= NDCR_SPARE_EN; /* enable spare by default */
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info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
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info->reg_ndcr |= (chip->page_shift == 6) ? NDCR_PG_PER_BLK : 0;
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info->reg_ndcr |= (mtd->writesize == 2048) ? NDCR_PAGE_SZ : 0;
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if (f->flash_width != 16 && f->flash_width != 8) {
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dev_err(&pdev->dev, "Only support 8bit and 16 bit!\n");
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return -EINVAL;
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}
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/* calculate addressing information */
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host->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
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if (f->num_blocks * f->page_per_block > 65536)
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host->row_addr_cycles = 3;
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else
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host->row_addr_cycles = 2;
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ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
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ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
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ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
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ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
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ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0;
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ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
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ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
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ndcr |= NDCR_SPARE_EN; /* enable spare by default */
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info->reg_ndcr = ndcr;
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pxa3xx_nand_set_timing(host, f->timing);
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return 0;
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}
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@ -1514,19 +1492,23 @@ static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info)
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kfree(info->data_buff);
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}
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static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
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static int pxa3xx_nand_sensing(struct pxa3xx_nand_host *host)
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{
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struct pxa3xx_nand_info *info = host->info_data;
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struct mtd_info *mtd;
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struct nand_chip *chip;
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const struct nand_sdr_timings *timings;
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int ret;
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mtd = info->host[info->cs]->mtd;
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chip = mtd->priv;
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/* use the common timing to make a try */
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ret = pxa3xx_nand_config_flash(info, &builtin_flash_types[0]);
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if (ret)
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return ret;
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timings = onfi_async_timing_mode_to_sdr_timings(0);
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if (IS_ERR(timings))
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return PTR_ERR(timings);
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pxa3xx_nand_set_sdr_timing(host, timings);
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chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
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ret = chip->waitfunc(mtd, chip);
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@ -1611,12 +1593,8 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
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struct pxa3xx_nand_info *info = host->info_data;
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struct platform_device *pdev = info->pdev;
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struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
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struct nand_flash_dev pxa3xx_flash_ids[2], *def = NULL;
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const struct pxa3xx_nand_flash *f = NULL;
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struct nand_chip *chip = mtd->priv;
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uint32_t id = -1;
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uint64_t chipsize;
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int i, ret, num;
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int ret;
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uint16_t ecc_strength, ecc_step;
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if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
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@ -1625,7 +1603,11 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
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/* Set a default chunk size */
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info->chunk_size = 512;
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ret = pxa3xx_nand_sensing(info);
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ret = pxa3xx_nand_config_flash(info);
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if (ret)
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return ret;
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ret = pxa3xx_nand_sensing(host);
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if (ret) {
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dev_info(&info->pdev->dev, "There is no chip on cs %d!\n",
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info->cs);
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@ -1633,50 +1615,6 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
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return ret;
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}
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chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0);
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id = *((uint16_t *)(info->data_buff));
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if (id != 0)
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dev_info(&info->pdev->dev, "Detect a flash id %x\n", id);
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else {
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dev_warn(&info->pdev->dev,
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"Read out ID 0, potential timing set wrong!!\n");
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return -EINVAL;
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}
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num = ARRAY_SIZE(builtin_flash_types) - 1;
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for (i = 0; i < num; i++) {
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f = &builtin_flash_types[i + 1];
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/* find the chip in default list */
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if (f->chip_id == id)
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break;
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}
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if (i >= (ARRAY_SIZE(builtin_flash_types) - 1)) {
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dev_err(&info->pdev->dev, "ERROR!! flash not defined!!!\n");
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return -EINVAL;
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}
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ret = pxa3xx_nand_config_flash(info, f);
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if (ret) {
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dev_err(&info->pdev->dev, "ERROR! Configure failed\n");
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return ret;
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}
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memset(pxa3xx_flash_ids, 0, sizeof(pxa3xx_flash_ids));
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pxa3xx_flash_ids[0].name = f->name;
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pxa3xx_flash_ids[0].dev_id = (f->chip_id >> 8) & 0xffff;
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pxa3xx_flash_ids[0].pagesize = f->page_size;
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chipsize = (uint64_t)f->num_blocks * f->page_per_block * f->page_size;
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pxa3xx_flash_ids[0].chipsize = chipsize >> 20;
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pxa3xx_flash_ids[0].erasesize = f->page_size * f->page_per_block;
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if (f->flash_width == 16)
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pxa3xx_flash_ids[0].options = NAND_BUSWIDTH_16;
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pxa3xx_flash_ids[1].name = NULL;
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def = pxa3xx_flash_ids;
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KEEP_CONFIG:
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info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
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if (info->reg_ndcr & NDCR_DWIDTH_M)
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@ -1686,9 +1624,18 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
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if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
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nand_writel(info, NDECCCTRL, 0x0);
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if (nand_scan_ident(mtd, 1, def))
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if (nand_scan_ident(mtd, 1, NULL))
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return -ENODEV;
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if (!pdata->keep_config) {
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ret = pxa3xx_nand_init(host);
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if (ret) {
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dev_err(&info->pdev->dev, "Failed to init nand: %d\n",
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ret);
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return ret;
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}
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}
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if (pdata->flash_bbt) {
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/*
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* We'll use a bad block table stored in-flash and don't
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