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PCI: thunder: Add PCIe host driver for ThunderX processors
The root complexes used to access off-chip PCIe devices (called PEM units in the hardware manuals) on some Cavium ThunderX processors require quirky access methods for the config space of the PCIe bridge. Add a driver to provide these config space accessor functions. Use the pci-host-common code to configure the PCI machinery. Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
David Daney
Bjorn Helgaas
parent
4e64dbe226
commit
f12b76e56a
43
Documentation/devicetree/bindings/pci/pci-thunder-pem.txt
Normal file
43
Documentation/devicetree/bindings/pci/pci-thunder-pem.txt
Normal file
@ -0,0 +1,43 @@
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* ThunderX PEM PCIe host controller
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Firmware-initialized PCI host controller found on some Cavium
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ThunderX processors.
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The properties and their meanings are identical to those described in
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host-generic-pci.txt except as listed below.
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Properties of the host controller node that differ from
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host-generic-pci.txt:
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- compatible : Must be "cavium,pci-host-thunder-pem"
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- reg : Two entries: First the configuration space for down
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stream devices base address and size, as accessed
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from the parent bus. Second, the register bank of
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the PEM device PCIe bridge.
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Example:
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pci@87e0,c2000000 {
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compatible = "cavium,pci-host-thunder-pem";
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device_type = "pci";
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msi-parent = <&its>;
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msi-map = <0 &its 0x10000 0x10000>;
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bus-range = <0x8f 0xc7>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <0x8880 0x8f000000 0x0 0x39000000>, /* Configuration space */
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<0x87e0 0xc2000000 0x0 0x00010000>; /* PEM space */
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ranges = <0x01000000 0x00 0x00020000 0x88b0 0x00020000 0x00 0x00010000>, /* I/O */
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<0x03000000 0x00 0x10000000 0x8890 0x10000000 0x0f 0xf0000000>, /* mem64 */
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<0x43000000 0x10 0x00000000 0x88a0 0x00000000 0x10 0x00000000>, /* mem64-pref */
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<0x03000000 0x87e0 0xc2f00000 0x87e0 0xc2000000 0x00 0x00100000>; /* mem64 PEM BAR4 */
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &gic0 0 0 0 24 4>, /* INTA */
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<0 0 0 2 &gic0 0 0 0 25 4>, /* INTB */
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<0 0 0 3 &gic0 0 0 0 26 4>, /* INTC */
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<0 0 0 4 &gic0 0 0 0 27 4>; /* INTD */
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};
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@ -8419,6 +8419,14 @@ L: linux-arm-msm@vger.kernel.org
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S: Maintained
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F: drivers/pci/host/*qcom*
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PCIE DRIVER FOR CAVIUM THUNDERX
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M: David Daney <david.daney@cavium.com>
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L: linux-pci@vger.kernel.org
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Supported
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F: Documentation/devicetree/bindings/pci/pci-thunder-*
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F: drivers/pci/host/pci-thunder-*
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PCMCIA SUBSYSTEM
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P: Linux PCMCIA Team
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L: linux-pcmcia@lists.infradead.org
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@ -195,4 +195,11 @@ config PCIE_QCOM
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PCIe controller uses the Designware core plus Qualcomm-specific
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hardware wrappers.
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config PCI_HOST_THUNDER_PEM
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bool "Cavium Thunder PCIe controller to off-chip devices"
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depends on OF && ARM64
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select PCI_HOST_COMMON
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help
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Say Y here if you want PCIe support for CN88XX Cavium Thunder SoCs.
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endmenu
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@ -23,3 +23,4 @@ obj-$(CONFIG_PCIE_ALTERA) += pcie-altera.o
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obj-$(CONFIG_PCIE_ALTERA_MSI) += pcie-altera-msi.o
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obj-$(CONFIG_PCI_HISI) += pcie-hisi.o
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obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
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obj-$(CONFIG_PCI_HOST_THUNDER_PEM) += pci-thunder-pem.o
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346
drivers/pci/host/pci-thunder-pem.c
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346
drivers/pci/host/pci-thunder-pem.c
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@ -0,0 +1,346 @@
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Copyright (C) 2015 - 2016 Cavium, Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/platform_device.h>
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#include "pci-host-common.h"
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#define PEM_CFG_WR 0x28
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#define PEM_CFG_RD 0x30
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struct thunder_pem_pci {
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struct gen_pci gen_pci;
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u32 ea_entry[3];
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void __iomem *pem_reg_base;
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};
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static void __iomem *thunder_pem_map_bus(struct pci_bus *bus,
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unsigned int devfn, int where)
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{
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struct gen_pci *pci = bus->sysdata;
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resource_size_t idx = bus->number - pci->cfg.bus_range->start;
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return pci->cfg.win[idx] + ((devfn << 16) | where);
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}
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static int thunder_pem_bridge_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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u64 read_val;
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struct thunder_pem_pci *pem_pci;
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struct gen_pci *pci = bus->sysdata;
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pem_pci = container_of(pci, struct thunder_pem_pci, gen_pci);
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if (devfn != 0 || where >= 2048) {
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*val = ~0;
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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/*
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* 32-bit accesses only. Write the address to the low order
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* bits of PEM_CFG_RD, then trigger the read by reading back.
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* The config data lands in the upper 32-bits of PEM_CFG_RD.
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*/
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read_val = where & ~3ull;
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writeq(read_val, pem_pci->pem_reg_base + PEM_CFG_RD);
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read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
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read_val >>= 32;
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/*
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* The config space contains some garbage, fix it up. Also
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* synthesize an EA capability for the BAR used by MSI-X.
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*/
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switch (where & ~3) {
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case 0x40:
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read_val &= 0xffff00ff;
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read_val |= 0x00007000; /* Skip MSI CAP */
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break;
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case 0x70: /* Express Cap */
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/* PME interrupt on vector 2*/
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read_val |= (2u << 25);
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break;
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case 0xb0: /* MSI-X Cap */
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/* TableSize=4, Next Cap is EA */
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read_val &= 0xc00000ff;
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read_val |= 0x0003bc00;
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break;
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case 0xb4:
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/* Table offset=0, BIR=0 */
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read_val = 0x00000000;
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break;
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case 0xb8:
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/* BPA offset=0xf0000, BIR=0 */
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read_val = 0x000f0000;
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break;
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case 0xbc:
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/* EA, 1 entry, no next Cap */
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read_val = 0x00010014;
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break;
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case 0xc0:
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/* DW2 for type-1 */
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read_val = 0x00000000;
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break;
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case 0xc4:
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/* Entry BEI=0, PP=0x00, SP=0xff, ES=3 */
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read_val = 0x80ff0003;
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break;
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case 0xc8:
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read_val = pem_pci->ea_entry[0];
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break;
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case 0xcc:
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read_val = pem_pci->ea_entry[1];
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break;
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case 0xd0:
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read_val = pem_pci->ea_entry[2];
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break;
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default:
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break;
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}
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read_val >>= (8 * (where & 3));
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switch (size) {
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case 1:
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read_val &= 0xff;
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break;
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case 2:
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read_val &= 0xffff;
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break;
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default:
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break;
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}
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*val = read_val;
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return PCIBIOS_SUCCESSFUL;
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}
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static int thunder_pem_config_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 *val)
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{
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struct gen_pci *pci = bus->sysdata;
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if (bus->number < pci->cfg.bus_range->start ||
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bus->number > pci->cfg.bus_range->end)
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* The first device on the bus is the PEM PCIe bridge.
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* Special case its config access.
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*/
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if (bus->number == pci->cfg.bus_range->start)
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return thunder_pem_bridge_read(bus, devfn, where, size, val);
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return pci_generic_config_read(bus, devfn, where, size, val);
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}
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/*
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* Some of the w1c_bits below also include read-only or non-writable
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* reserved bits, this makes the code simpler and is OK as the bits
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* are not affected by writing zeros to them.
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*/
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static u32 thunder_pem_bridge_w1c_bits(int where)
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{
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u32 w1c_bits = 0;
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switch (where & ~3) {
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case 0x04: /* Command/Status */
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case 0x1c: /* Base and I/O Limit/Secondary Status */
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w1c_bits = 0xff000000;
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break;
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case 0x44: /* Power Management Control and Status */
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w1c_bits = 0xfffffe00;
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break;
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case 0x78: /* Device Control/Device Status */
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case 0x80: /* Link Control/Link Status */
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case 0x88: /* Slot Control/Slot Status */
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case 0x90: /* Root Status */
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case 0xa0: /* Link Control 2 Registers/Link Status 2 */
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w1c_bits = 0xffff0000;
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break;
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case 0x104: /* Uncorrectable Error Status */
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case 0x110: /* Correctable Error Status */
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case 0x130: /* Error Status */
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case 0x160: /* Link Control 4 */
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w1c_bits = 0xffffffff;
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break;
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default:
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break;
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}
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return w1c_bits;
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}
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static int thunder_pem_bridge_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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struct gen_pci *pci = bus->sysdata;
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struct thunder_pem_pci *pem_pci;
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u64 write_val, read_val;
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u32 mask = 0;
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pem_pci = container_of(pci, struct thunder_pem_pci, gen_pci);
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if (devfn != 0 || where >= 2048)
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* 32-bit accesses only. If the write is for a size smaller
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* than 32-bits, we must first read the 32-bit value and merge
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* in the desired bits and then write the whole 32-bits back
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* out.
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*/
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switch (size) {
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case 1:
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read_val = where & ~3ull;
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writeq(read_val, pem_pci->pem_reg_base + PEM_CFG_RD);
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read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
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read_val >>= 32;
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mask = ~(0xff << (8 * (where & 3)));
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read_val &= mask;
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val = (val & 0xff) << (8 * (where & 3));
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val |= (u32)read_val;
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break;
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case 2:
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read_val = where & ~3ull;
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writeq(read_val, pem_pci->pem_reg_base + PEM_CFG_RD);
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read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
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read_val >>= 32;
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mask = ~(0xffff << (8 * (where & 3)));
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read_val &= mask;
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val = (val & 0xffff) << (8 * (where & 3));
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val |= (u32)read_val;
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break;
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default:
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break;
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}
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/*
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* By expanding the write width to 32 bits, we may
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* inadvertently hit some W1C bits that were not intended to
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* be written. Calculate the mask that must be applied to the
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* data to be written to avoid these cases.
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*/
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if (mask) {
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u32 w1c_bits = thunder_pem_bridge_w1c_bits(where);
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if (w1c_bits) {
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mask &= w1c_bits;
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val &= ~mask;
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}
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}
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/*
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* Low order bits are the config address, the high order 32
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* bits are the data to be written.
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*/
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write_val = where & ~3ull;
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write_val |= (((u64)val) << 32);
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writeq(write_val, pem_pci->pem_reg_base + PEM_CFG_WR);
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return PCIBIOS_SUCCESSFUL;
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}
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static int thunder_pem_config_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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struct gen_pci *pci = bus->sysdata;
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if (bus->number < pci->cfg.bus_range->start ||
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bus->number > pci->cfg.bus_range->end)
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return PCIBIOS_DEVICE_NOT_FOUND;
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/*
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* The first device on the bus is the PEM PCIe bridge.
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* Special case its config access.
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*/
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if (bus->number == pci->cfg.bus_range->start)
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return thunder_pem_bridge_write(bus, devfn, where, size, val);
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return pci_generic_config_write(bus, devfn, where, size, val);
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}
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static struct gen_pci_cfg_bus_ops thunder_pem_bus_ops = {
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.bus_shift = 24,
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.ops = {
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.map_bus = thunder_pem_map_bus,
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.read = thunder_pem_config_read,
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.write = thunder_pem_config_write,
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}
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};
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static const struct of_device_id thunder_pem_of_match[] = {
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{ .compatible = "cavium,pci-host-thunder-pem",
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.data = &thunder_pem_bus_ops },
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{ },
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};
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MODULE_DEVICE_TABLE(of, thunder_pem_of_match);
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static int thunder_pem_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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const struct of_device_id *of_id;
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resource_size_t bar4_start;
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struct resource *res_pem;
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struct thunder_pem_pci *pem_pci;
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pem_pci = devm_kzalloc(dev, sizeof(*pem_pci), GFP_KERNEL);
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if (!pem_pci)
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return -ENOMEM;
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of_id = of_match_node(thunder_pem_of_match, dev->of_node);
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pem_pci->gen_pci.cfg.ops = (struct gen_pci_cfg_bus_ops *)of_id->data;
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/*
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* The second register range is the PEM bridge to the PCIe
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* bus. It has a different config access method than those
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* devices behind the bridge.
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*/
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res_pem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!res_pem) {
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dev_err(dev, "missing \"reg[1]\"property\n");
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return -EINVAL;
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}
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pem_pci->pem_reg_base = devm_ioremap(dev, res_pem->start, 0x10000);
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if (!pem_pci->pem_reg_base)
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return -ENOMEM;
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/*
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* The MSI-X BAR for the PEM and AER interrupts is located at
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* a fixed offset from the PEM register base. Generate a
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* fragment of the synthesized Enhanced Allocation capability
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* structure here for the BAR.
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*/
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bar4_start = res_pem->start + 0xf00000;
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pem_pci->ea_entry[0] = (u32)bar4_start | 2;
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pem_pci->ea_entry[1] = (u32)(res_pem->end - bar4_start) & ~3u;
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pem_pci->ea_entry[2] = (u32)(bar4_start >> 32);
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return pci_host_common_probe(pdev, &pem_pci->gen_pci);
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}
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static struct platform_driver thunder_pem_driver = {
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.driver = {
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.name = KBUILD_MODNAME,
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.of_match_table = thunder_pem_of_match,
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},
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.probe = thunder_pem_probe,
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};
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module_platform_driver(thunder_pem_driver);
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MODULE_DESCRIPTION("Thunder PEM PCIe host driver");
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MODULE_LICENSE("GPL v2");
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