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crypto: caam - fix snooping for write transactions
HW coherency won't work properly for CAAM write transactions if AWCACHE is left to default (POR) value - 4'b0001. It has to be programmed to 4'b0010, i.e. AXI3 Cacheable bit set. For platforms that have HW coherency support: -PPC-based: the update has no effect; CAAM coherency already works due to the IOMMU (PAMU) driver setting the correct memory coherency attributes -ARM-based: the update fixes cache coherency issues, since IOMMU (SMMU) driver is not programmed to behave similar to PAMU Signed-off-by: Horia Geant? <horia.geanta@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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@ -444,8 +444,9 @@ static int caam_probe(struct platform_device *pdev)
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* Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
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* long pointers in master configuration register
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*/
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setbits32(&ctrl->mcr, MCFGR_WDENABLE |
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(sizeof(dma_addr_t) == sizeof(u64) ? MCFGR_LONG_PTR : 0));
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clrsetbits_be32(&ctrl->mcr, MCFGR_AWCACHE_MASK, MCFGR_AWCACHE_CACH |
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MCFGR_WDENABLE | (sizeof(dma_addr_t) == sizeof(u64) ?
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MCFGR_LONG_PTR : 0));
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/*
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* Read the Compile Time paramters and SCFGR to determine
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@ -395,10 +395,16 @@ struct caam_ctrl {
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/* AXI read cache control */
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#define MCFGR_ARCACHE_SHIFT 12
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#define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT)
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#define MCFGR_ARCACHE_BUFF (0x1 << MCFGR_ARCACHE_SHIFT)
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#define MCFGR_ARCACHE_CACH (0x2 << MCFGR_ARCACHE_SHIFT)
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#define MCFGR_ARCACHE_RALL (0x4 << MCFGR_ARCACHE_SHIFT)
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/* AXI write cache control */
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#define MCFGR_AWCACHE_SHIFT 8
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#define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT)
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#define MCFGR_AWCACHE_BUFF (0x1 << MCFGR_AWCACHE_SHIFT)
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#define MCFGR_AWCACHE_CACH (0x2 << MCFGR_AWCACHE_SHIFT)
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#define MCFGR_AWCACHE_WALL (0x8 << MCFGR_AWCACHE_SHIFT)
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/* AXI pipeline depth */
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#define MCFGR_AXIPIPE_SHIFT 4
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