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drm/amd/powerplay: update driver if file for sienna_cichlid

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Update sienna_cichlid driver if header file to match pptable changes.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Likun Gao 2020-06-24 14:03:48 +08:00 committed by Alex Deucher
parent 969c8d16a2
commit f0f3d68e67
3 changed files with 10 additions and 11 deletions
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12
drivers/gpu/drm/amd/powerplay/inc/smu11_driver_if_sienna_cichlid.h
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@ -27,7 +27,7 @@
// *** IMPORTANT *** // *** IMPORTANT ***
// SMU TEAM: Always increment the interface version if // SMU TEAM: Always increment the interface version if
// any structure is changed in this file // any structure is changed in this file
#define SMU11_DRIVER_IF_VERSION 0x31 #define SMU11_DRIVER_IF_VERSION 0x32
#define PPTABLE_Sienna_Cichlid_SMU_VERSION 4 #define PPTABLE_Sienna_Cichlid_SMU_VERSION 4
@ -865,8 +865,7 @@ typedef struct {
uint16_t DfllGfxclkSpreadFreq; // kHz uint16_t DfllGfxclkSpreadFreq; // kHz
// UCLK Spread Spectrum // UCLK Spread Spectrum
uint8_t UclkSpreadEnabled; // on or off uint16_t UclkSpreadPadding;
uint8_t UclkSpreadPercent; // Q4.4
uint16_t UclkSpreadFreq; // kHz uint16_t UclkSpreadFreq; // kHz
// FCLK Spread Spectrum // FCLK Spread Spectrum
@ -896,8 +895,11 @@ typedef struct {
uint8_t VddqOffEnabled; uint8_t VddqOffEnabled;
uint8_t PaddingUmcFlags[2]; uint8_t PaddingUmcFlags[2];
// UCLK Spread Spectrum
uint8_t UclkSpreadPercent[16];
// SECTION: Board Reserved // SECTION: Board Reserved
uint32_t BoardReserved[15]; uint32_t BoardReserved[11];
// SECTION: Structure Padding // SECTION: Structure Padding
@ -936,10 +938,12 @@ typedef struct {
int16_t OverDrivePct; // % int16_t OverDrivePct; // %
uint16_t FanMaximumRpm; uint16_t FanMaximumRpm;
uint16_t FanMinimumPwm; uint16_t FanMinimumPwm;
uint16_t FanAcousticLimitRpm;
uint16_t FanTargetTemperature; // Degree Celcius uint16_t FanTargetTemperature; // Degree Celcius
uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS]; uint8_t FanLinearPwmPoints[NUM_OD_FAN_MAX_POINTS];
uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS]; uint8_t FanLinearTempPoints[NUM_OD_FAN_MAX_POINTS];
uint16_t MaxOpTemp; // Degree Celcius uint16_t MaxOpTemp; // Degree Celcius
uint16_t Padding_16[1];
uint8_t FanZeroRpmEnable; uint8_t FanZeroRpmEnable;
uint8_t FanZeroRpmStopTemp; uint8_t FanZeroRpmStopTemp;
uint8_t FanMode; uint8_t FanMode;

2
drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h
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@ -30,7 +30,7 @@
#define SMU11_DRIVER_IF_VERSION_NV10 0x36 #define SMU11_DRIVER_IF_VERSION_NV10 0x36
#define SMU11_DRIVER_IF_VERSION_NV12 0x33 #define SMU11_DRIVER_IF_VERSION_NV12 0x33
#define SMU11_DRIVER_IF_VERSION_NV14 0x36 #define SMU11_DRIVER_IF_VERSION_NV14 0x36
#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x31 #define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x32
/* MP Apertures */ /* MP Apertures */
#define MP0_Public 0x03800000 #define MP0_Public 0x03800000

7
drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
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@ -2404,8 +2404,7 @@ static void sienna_cichlid_dump_pptable(struct smu_context *smu)
dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent); dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq); dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n", pptable->DfllGfxclkSpreadFreq);
dev_info(smu->adev->dev, "UclkSpreadEnabled = 0x%x\n", pptable->UclkSpreadEnabled); dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
dev_info(smu->adev->dev, "UclkSpreadPercent = 0x%x\n", pptable->UclkSpreadPercent);
dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq); dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled); dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
@ -2450,10 +2449,6 @@ static void sienna_cichlid_dump_pptable(struct smu_context *smu)
dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]); dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]); dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]); dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
dev_info(smu->adev->dev, "BoardReserved[11] = 0x%x\n", pptable->BoardReserved[11]);
dev_info(smu->adev->dev, "BoardReserved[12] = 0x%x\n", pptable->BoardReserved[12]);
dev_info(smu->adev->dev, "BoardReserved[13] = 0x%x\n", pptable->BoardReserved[13]);
dev_info(smu->adev->dev, "BoardReserved[14] = 0x%x\n", pptable->BoardReserved[14]);
dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]); dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]); dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);