AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-12-28 11:18:45 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

drm/amd/display: Don't reserve pipe for underlay on ASIC without underlay

Browse Source 
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Jordan Lazare <Jordan.Lazare@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Harry Wentland 2017-01-23 11:49:24 -05:00 committed by Alex Deucher
parent adc9b14139
commit f0e3db90a6
5 changed files with 7 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/amd/display/dc/core/dc.c
View File

@ -621,7 +621,7 @@ struct dc *dc_create(const struct dc_init_data *init_params)
core_dc->hwss.init_hw(core_dc);
full_pipe_count = core_dc->res_pool->pipe_count;
if (core_dc->res_pool->underlay_pipe_index >= 0)
if (core_dc->res_pool->underlay_pipe_index != NO_UNDERLAY_PIPE)
full_pipe_count--;
core_dc->public.caps.max_streams = min(
full_pipe_count,

4
drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
View File

@ -934,7 +934,7 @@ static bool construct(
pool->base.res_cap = &res_cap;
pool->base.funcs = &dce100_res_pool_funcs;
pool->base.underlay_pipe_index = -1;
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
bp = ctx->dc_bios;
@ -1004,7 +1004,7 @@ static bool construct(
/*************************************************
* Resource + asic cap harcoding *
*************************************************/
pool->base.underlay_pipe_index = -1;
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
pool->base.pipe_count = res_cap.num_timing_generator;
dc->public.caps.max_downscale_ratio = 200;
dc->public.caps.i2c_speed_in_khz = 40;

2
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
View File

@ -1243,7 +1243,7 @@ static bool construct(
/*************************************************
* Resource + asic cap harcoding *
*************************************************/
pool->base.underlay_pipe_index = -1;
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
dc->public.caps.max_downscale_ratio = 200;
dc->public.caps.i2c_speed_in_khz = 100;

2
drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
View File

@ -931,7 +931,7 @@ static bool construct(
/*************************************************
* Resource + asic cap harcoding *
*************************************************/
pool->base.underlay_pipe_index = -1;
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
pool->base.pipe_count = res_cap.num_timing_generator;
dc->public.caps.max_downscale_ratio = 200;
dc->public.caps.i2c_speed_in_khz = 40;

2
drivers/gpu/drm/amd/display/dc/inc/core_types.h
View File

@ -230,6 +230,8 @@ struct audio_support{
bool hdmi_audio_native;
};
#define NO_UNDERLAY_PIPE -1
struct resource_pool {
struct mem_input *mis[MAX_PIPES];
struct input_pixel_processor *ipps[MAX_PIPES];