mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-04 06:56:41 +07:00
iwlwifi: fix 64bit platform firmware loading
This patch fixes loading firmware from memory above 32bit. Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com> Signed-off-by: Zhu Yi <yi.zhu@intel.com> Acked-by: Marcel Holtmann <holtmann@linux.intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
parent
1d3e6c6134
commit
f0b9f5cb4a
@ -578,14 +578,11 @@ static int iwl5000_load_section(struct iwl_priv *priv,
|
|||||||
FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
|
FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
|
||||||
phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
|
phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
|
||||||
|
|
||||||
/* FIME: write the MSB of the phy_addr in CTRL1
|
|
||||||
* iwl_write_direct32(priv,
|
|
||||||
IWL_FH_TFDIB_CTRL1_REG(IWL_FH_SRVC_CHNL),
|
|
||||||
((phy_addr & MSB_MSK)
|
|
||||||
<< FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_count);
|
|
||||||
*/
|
|
||||||
iwl_write_direct32(priv,
|
iwl_write_direct32(priv,
|
||||||
FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), byte_cnt);
|
FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
|
||||||
|
(iwl_get_dma_hi_address(phy_addr)
|
||||||
|
<< FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
|
||||||
|
|
||||||
iwl_write_direct32(priv,
|
iwl_write_direct32(priv,
|
||||||
FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
|
FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
|
||||||
1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
|
1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
|
||||||
|
@ -287,6 +287,7 @@
|
|||||||
|
|
||||||
#define FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
|
#define FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE (0x01000000)
|
||||||
|
|
||||||
|
#define FH_MEM_TFDIB_REG1_ADDR_BITSHIFT 28
|
||||||
|
|
||||||
/**
|
/**
|
||||||
* Transmit DMA Channel Control/Status Registers (TCSR)
|
* Transmit DMA Channel Control/Status Registers (TCSR)
|
||||||
|
Loading…
Reference in New Issue
Block a user