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drm/amd/powerplay: add get_temperature interface for raven
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -35,6 +35,7 @@
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#include "rv_hwmgr.h"
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#include "power_state.h"
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#include "rv_smumgr.h"
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#include "pp_soc15.h"
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#define RAVEN_MAX_DEEPSLEEP_DIVIDER_ID 5
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#define RAVEN_MINIMUM_ENGINE_CLOCK 800 //8Mhz, the low boundary of engine clock allowed on this chip
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@ -42,7 +43,6 @@
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#define RAVEN_DISPCLK_BYPASS_THRESHOLD 10000 //100mhz
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#define SMC_RAM_END 0x40000
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static const unsigned long PhwRaven_Magic = (unsigned long) PHM_Rv_Magic;
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int rv_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
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struct pp_display_clock_request *clock_req);
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@ -613,6 +613,7 @@ static int rv_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
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hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
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rv_init_vq_budget_table(hwmgr);
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return result;
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}
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@ -981,10 +982,32 @@ static int rv_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_c
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return -EINVAL;
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}
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static int rv_thermal_get_temperature(struct pp_hwmgr *hwmgr)
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{
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uint32_t reg_offset = soc15_get_register_offset(THM_HWID, 0,
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mmTHM_TCON_CUR_TMP_BASE_IDX, mmTHM_TCON_CUR_TMP);
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uint32_t reg_value = cgs_read_register(hwmgr->device, reg_offset);
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int cur_temp =
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(reg_value & THM_TCON_CUR_TMP__CUR_TEMP_MASK) >> THM_TCON_CUR_TMP__CUR_TEMP__SHIFT;
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if (cur_temp & THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK)
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cur_temp = ((cur_temp / 8) - 49) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
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else
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cur_temp = (cur_temp / 8) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
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return cur_temp;
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}
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static int rv_read_sensor(struct pp_hwmgr *hwmgr, int idx,
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void *value, int *size)
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{
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return -EINVAL;
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switch (idx) {
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case AMDGPU_PP_SENSOR_GPU_TEMP:
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*((uint32_t *)value) = rv_thermal_get_temperature(hwmgr);
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return 0;
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default:
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return -EINVAL;
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}
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}
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static const struct pp_hwmgr_func rv_hwmgr_funcs = {
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