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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 16:48:18 +07:00
net: hns3: stop handling command queue while resetting VF
According to hardware's description, after the reset occurs, the driver needs to re-initialize the command queue before sending and receiving any commands. Therefore, the VF's driver needs to identify the command queue needs to re-initialize with HCLGEVF_STATE_CMD_DISABLE, and does not allow sending or receiving commands before the re-initialization. Signed-off-by: Huazhong Tan <tanhuazhong@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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parent
b90fcc5bd9
commit
ef5f8e507e
drivers/net/ethernet/hisilicon/hns3/hns3vf
@ -189,7 +189,8 @@ int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclgevf_desc *desc, int num)
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spin_lock_bh(&hw->cmq.csq.lock);
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if (num > hclgevf_ring_space(&hw->cmq.csq)) {
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if (num > hclgevf_ring_space(&hw->cmq.csq) ||
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test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) {
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spin_unlock_bh(&hw->cmq.csq.lock);
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return -EBUSY;
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}
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@ -338,6 +339,16 @@ int hclgevf_cmd_init(struct hclgevf_dev *hdev)
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spin_unlock_bh(&hdev->hw.cmq.crq.lock);
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spin_unlock_bh(&hdev->hw.cmq.csq.lock);
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clear_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
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/* Check if there is new reset pending, because the higher level
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* reset may happen when lower level reset is being processed.
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*/
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if (hclgevf_is_reset_pending(hdev)) {
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set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
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return -EBUSY;
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}
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/* get firmware version */
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ret = hclgevf_cmd_query_firmware_version(&hdev->hw, &version);
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if (ret) {
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@ -1162,6 +1162,8 @@ static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev)
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break;
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}
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set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
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dev_info(&hdev->pdev->dev, "prepare reset(%d) wait done, ret:%d\n",
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hdev->reset_type, ret);
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@ -1467,6 +1469,7 @@ static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev,
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"receive reset interrupt 0x%x!\n", rst_ing_reg);
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set_bit(HNAE3_VF_RESET, &hdev->reset_pending);
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set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
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set_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state);
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cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RST_INT_B);
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*clearval = cmdq_src_reg;
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return HCLGEVF_VECTOR0_EVENT_RST;
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@ -79,6 +79,7 @@ enum hclgevf_states {
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HCLGEVF_STATE_RST_HANDLING,
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HCLGEVF_STATE_MBX_SERVICE_SCHED,
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HCLGEVF_STATE_MBX_HANDLING,
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HCLGEVF_STATE_CMD_DISABLE,
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};
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#define HCLGEVF_MPF_ENBALE 1
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@ -212,6 +213,11 @@ struct hclgevf_dev {
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u32 flag;
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};
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static inline bool hclgevf_is_reset_pending(struct hclgevf_dev *hdev)
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{
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return !!hdev->reset_pending;
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}
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int hclgevf_send_mbx_msg(struct hclgevf_dev *hdev, u16 code, u16 subcode,
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const u8 *msg_data, u8 msg_len, bool need_resp,
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u8 *resp_data, u16 resp_len);
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@ -40,6 +40,9 @@ static int hclgevf_get_mbx_resp(struct hclgevf_dev *hdev, u16 code0, u16 code1,
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}
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while ((!hdev->mbx_resp.received_resp) && (i < HCLGEVF_MAX_TRY_TIMES)) {
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if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state))
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return -EIO;
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udelay(HCLGEVF_SLEEP_USCOEND);
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i++;
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}
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@ -148,6 +151,11 @@ void hclgevf_mbx_handler(struct hclgevf_dev *hdev)
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crq = &hdev->hw.cmq.crq;
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while (!hclgevf_cmd_crq_empty(&hdev->hw)) {
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if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) {
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dev_info(&hdev->pdev->dev, "vf crq need init\n");
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return;
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}
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desc = &crq->desc[crq->next_to_use];
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req = (struct hclge_mbx_pf_to_vf_cmd *)desc->data;
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@ -249,6 +257,12 @@ void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev)
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/* process all the async queue messages */
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while (tail != hdev->arq.head) {
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if (test_bit(HCLGEVF_STATE_CMD_DISABLE, &hdev->state)) {
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dev_info(&hdev->pdev->dev,
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"vf crq need init in async\n");
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return;
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}
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msg_q = hdev->arq.msg_q[hdev->arq.head];
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switch (msg_q[0]) {
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