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drm/i915/tgl: Disable preemption while being debugged

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We see failures where the context continues executing past a
preemption event, eventually leading to situations where a request has
executed before we have event submitted it to HW! It seems like tgl is
ignoring our RING_TAIL updates, but more likely is that there is a
missing update required for our semaphore waits around preemption.

v2: And disable internal semaphore usage

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190912132313.12751-1-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson 2019-09-12 14:23:13 +01:00
parent 16ffe73c18
commit ee73e2795b
2 changed files with 4 additions and 0 deletions
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3
drivers/gpu/drm/i915/gt/intel_lrc.c
View File

@ -2939,6 +2939,9 @@ void intel_execlists_set_default_submission(struct intel_engine_cs *engine)
engine->flags |= I915_ENGINE_HAS_PREEMPTION;
}
if (INTEL_GEN(engine->i915) >= 12) /* XXX disabled for debugging */
engine->flags &= ~I915_ENGINE_HAS_SEMAPHORES;
if (engine->class != COPY_ENGINE_CLASS && INTEL_GEN(engine->i915) >= 12)
engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO;
}

1
drivers/gpu/drm/i915/i915_pci.c
View File

@ -798,6 +798,7 @@ static const struct intel_device_info intel_tigerlake_12_info = {
.engine_mask =
BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
.has_rc6 = false, /* XXX disabled for debugging */
.has_logical_ring_preemption = false, /* XXX disabled for debugging */
};
#undef GEN