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drm/i915: Remove reset_counter from intel_crtc.
With the removal of cs-based flips all mmio waits will finish without requiring the reset counter, because the waits will complete during gpu reset. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1463490484-19540-16-git-send-email-maarten.lankhorst@linux.intel.com Reviewed-by: Patrik Jakobsson <patrik.jakobsson@linux.intel.com>
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@ -3179,14 +3179,6 @@ void intel_finish_reset(struct drm_i915_private *dev_priv)
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static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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unsigned reset_counter;
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reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error);
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if (intel_crtc->reset_counter != reset_counter)
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return false;
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return !list_empty_careful(&to_intel_crtc(crtc)->flip_work);
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}
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@ -11179,7 +11171,6 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
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intel_fbc_pre_update(intel_crtc);
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intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error);
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schedule_work(&work->mmio_work);
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mutex_unlock(&dev->struct_mutex);
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@ -659,9 +659,6 @@ struct intel_crtc {
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struct intel_crtc_state *config;
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/* reset counter value when the last flip was submitted */
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unsigned int reset_counter;
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/* Access to these should be protected by dev_priv->irq_lock. */
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bool cpu_fifo_underrun_disabled;
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bool pch_fifo_underrun_disabled;
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