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drm/amdgpu: add reset_method asic callback for soc15
APUs only support mode2 reset. dGPUs use either mode1 or baco depending on various conditions. Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -465,12 +465,14 @@ static int soc15_asic_baco_reset(struct amdgpu_device *adev)
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return 0;
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}
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static int soc15_asic_reset(struct amdgpu_device *adev)
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static enum amd_reset_method
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soc15_asic_reset_method(struct amdgpu_device *adev)
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{
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int ret;
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bool baco_reset;
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switch (adev->asic_type) {
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case CHIP_RAVEN:
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return AMD_RESET_METHOD_MODE2;
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case CHIP_VEGA10:
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case CHIP_VEGA12:
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soc15_asic_get_baco_capability(adev, &baco_reset);
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@ -494,6 +496,16 @@ static int soc15_asic_reset(struct amdgpu_device *adev)
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}
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if (baco_reset)
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return AMD_RESET_METHOD_BACO;
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else
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return AMD_RESET_METHOD_MODE1;
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}
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static int soc15_asic_reset(struct amdgpu_device *adev)
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{
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int ret;
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if (soc15_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)
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ret = soc15_asic_baco_reset(adev);
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else
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ret = soc15_asic_mode1_reset(adev);
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@ -807,6 +819,7 @@ static const struct amdgpu_asic_funcs soc15_asic_funcs =
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.read_bios_from_rom = &soc15_read_bios_from_rom,
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.read_register = &soc15_read_register,
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.reset = &soc15_asic_reset,
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.reset_method = &soc15_asic_reset_method,
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.set_vga_state = &soc15_vga_set_state,
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.get_xclk = &soc15_get_xclk,
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.set_uvd_clocks = &soc15_set_uvd_clocks,
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