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drm/amdgpu: value of amdgpu_sriov_vf cannot be set into F32_POLL_ENABLE
amdgpu_sriov_vf would return 0x0 or 0x4 to indicate if sriov. but F32_POLL_ENABLE need 0x0 or 0x1 to determine if enabled. set 0x4 into F32_POLL_ENABLE would make SDMA0_GFX_RB_WPTR_POLL_CNTL not working. Signed-off-by: Wentao Lou <Wentao.Lou@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -849,7 +849,7 @@ static void sdma_v4_0_gfx_resume(struct amdgpu_device *adev, unsigned int i)
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wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL);
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wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
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SDMA0_GFX_RB_WPTR_POLL_CNTL,
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F32_POLL_ENABLE, amdgpu_sriov_vf(adev));
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F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
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WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
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/* enable DMA RB */
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@ -940,7 +940,7 @@ static void sdma_v4_0_page_resume(struct amdgpu_device *adev, unsigned int i)
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wptr_poll_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL);
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wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
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SDMA0_PAGE_RB_WPTR_POLL_CNTL,
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F32_POLL_ENABLE, amdgpu_sriov_vf(adev));
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F32_POLL_ENABLE, amdgpu_sriov_vf(adev)? 1 : 0);
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WREG32_SDMA(i, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, wptr_poll_cntl);
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/* enable DMA RB */
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