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ARM: bL_switcher: do not hardcode GIC IDs in the code
Currently, GIC IDs are hardcoded making the code dependent on the 4+4 b.L configuration. Let's allow for GIC IDs to be discovered upon switcher initialization to support other b.L configurations such as the 1+1 one, or 2+3 as on the VExpress TC2. Signed-off-by: Nicolas Pitre <nico@linaro.org>
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@ -110,6 +110,8 @@ static int bL_switchpoint(unsigned long _arg)
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* Generic switcher interface
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*/
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static unsigned int bL_gic_id[MAX_CPUS_PER_CLUSTER][MAX_NR_CLUSTERS];
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/*
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* bL_switch_to - Switch to a specific cluster for the current CPU
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* @new_cluster_id: the ID of the cluster to switch to.
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@ -159,7 +161,7 @@ static int bL_switch_to(unsigned int new_cluster_id)
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this_cpu = smp_processor_id();
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/* redirect GIC's SGIs to our counterpart */
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gic_migrate_target(cpuid + ib_cluster*4);
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gic_migrate_target(bL_gic_id[cpuid][ib_cluster]);
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/*
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* Raise a SGI on the inbound CPU to make sure it doesn't stall
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@ -332,6 +334,16 @@ static int __init bL_switcher_halve_cpus(void)
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cluster = (cpu_logical_map(i) >> 8) & 0xff;
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if (cpumask_test_cpu(cpu, &common_mask)) {
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/* Let's take note of the GIC ID for this CPU */
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int gic_id = gic_get_cpu_id(i);
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if (gic_id < 0) {
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pr_err("%s: bad GIC ID for CPU %d\n", __func__, i);
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return -EINVAL;
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}
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bL_gic_id[cpu][cluster] = gic_id;
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pr_info("GIC ID for CPU %u cluster %u is %u\n",
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cpu, cluster, gic_id);
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/*
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* We keep only those logical CPUs which number
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* is equal to their physical CPU number. This is
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@ -667,6 +667,27 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
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#endif
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#ifdef CONFIG_BL_SWITCHER
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/*
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* gic_get_cpu_id - get the CPU interface ID for the specified CPU
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*
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* @cpu: the logical CPU number to get the GIC ID for.
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*
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* Return the CPU interface ID for the given logical CPU number,
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* or -1 if the CPU number is too large or the interface ID is
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* unknown (more than one bit set).
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*/
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int gic_get_cpu_id(unsigned int cpu)
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{
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unsigned int cpu_bit;
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if (cpu >= NR_GIC_CPU_IF)
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return -1;
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cpu_bit = gic_cpu_map[cpu];
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if (cpu_bit & (cpu_bit - 1))
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return -1;
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return __ffs(cpu_bit);
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}
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/*
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* gic_migrate_target - migrate IRQs to another CPU interface
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*
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@ -75,6 +75,7 @@ static inline void gic_init(unsigned int nr, int start,
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gic_init_bases(nr, start, dist, cpu, 0, NULL);
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}
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int gic_get_cpu_id(unsigned int cpu);
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void gic_migrate_target(unsigned int new_cpu_id);
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#endif /* __ASSEMBLY */
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