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drm/amdgpu/gfx9: enable/disable sck slowdown thru rlc-smu handshake
Required for proper powergating operation. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1903,6 +1903,44 @@ static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
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}
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}
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static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t data = 0;
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uint32_t default_data = 0;
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default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
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if (enable == true) {
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data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
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if (default_data != data)
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WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
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} else {
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data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PU_ENABLE_MASK;
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if(default_data != data)
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WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
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}
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}
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static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
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bool enable)
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{
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uint32_t data = 0;
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uint32_t default_data = 0;
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default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
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if (enable == true) {
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data |= RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
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if(default_data != data)
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WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
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} else {
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data &= ~RLC_PG_CNTL__SMU_CLK_SLOWDOWN_ON_PD_ENABLE_MASK;
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if(default_data != data)
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WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
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}
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}
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static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
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{
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if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
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@ -1919,6 +1957,13 @@ static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
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WREG32(mmRLC_JUMP_TABLE_RESTORE,
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adev->gfx.rlc.cp_table_gpu_addr >> 8);
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gfx_v9_0_init_gfx_power_gating(adev);
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if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
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gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
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gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
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} else {
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gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
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gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
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}
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}
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}
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}
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