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PCI: Remove MRRS modification from MPS setting code
Modifying the Maximum Read Request Size to 0 (value of 128Bytes) has massive negative ramifications on some devices. Without knowing which devices have this issue, do not modify from the default value when walking the PCI-E bus in pcie_bus_safe mode. Also, make pcie_bus_safe the default procedure. Tested-by: Sven Schnelle <svens@stackframe.org> Tested-by: Simon Kirby <sim@hostway.ca> Tested-by: Stephen M. Cameron <scameron@beardog.cce.hp.com> Reported-and-tested-by: Eric Dumazet <eric.dumazet@gmail.com> Reported-and-tested-by: Niels Ole Salscheider <niels_ole@salscheider-online.de> References: https://bugzilla.kernel.org/show_bug.cgi?id=42162 Signed-off-by: Jon Mason <mason@myri.com> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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@ -77,7 +77,7 @@ unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
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unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
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unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
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enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PERFORMANCE;
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enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_SAFE;
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/*
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* The default CLS is used if arch didn't set CLS explicitly and not
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@ -1396,34 +1396,37 @@ static void pcie_write_mps(struct pci_dev *dev, int mps)
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static void pcie_write_mrrs(struct pci_dev *dev, int mps)
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{
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int rc, mrrs;
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int rc, mrrs, dev_mpss;
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if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
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int dev_mpss = 128 << dev->pcie_mpss;
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/* In the "safe" case, do not configure the MRRS. There appear to be
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* issues with setting MRRS to 0 on a number of devices.
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*/
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/* For Max performance, the MRRS must be set to the largest
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* supported value. However, it cannot be configured larger
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* than the MPS the device or the bus can support. This assumes
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* that the largest MRRS available on the device cannot be
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* smaller than the device MPSS.
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*/
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mrrs = mps < dev_mpss ? mps : dev_mpss;
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} else
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/* In the "safe" case, configure the MRRS for fairness on the
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* bus by making all devices have the same size
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*/
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mrrs = mps;
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if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
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return;
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dev_mpss = 128 << dev->pcie_mpss;
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/* For Max performance, the MRRS must be set to the largest supported
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* value. However, it cannot be configured larger than the MPS the
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* device or the bus can support. This assumes that the largest MRRS
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* available on the device cannot be smaller than the device MPSS.
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*/
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mrrs = min(mps, dev_mpss);
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/* MRRS is a R/W register. Invalid values can be written, but a
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* subsiquent read will verify if the value is acceptable or not.
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* subsequent read will verify if the value is acceptable or not.
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* If the MRRS value provided is not acceptable (e.g., too large),
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* shrink the value until it is acceptable to the HW.
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*/
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while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
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dev_warn(&dev->dev, "Attempting to modify the PCI-E MRRS value"
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" to %d. If any issues are encountered, please try "
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"running with pci=pcie_bus_safe\n", mrrs);
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rc = pcie_set_readrq(dev, mrrs);
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if (rc)
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dev_err(&dev->dev, "Failed attempting to set the MRRS\n");
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dev_err(&dev->dev,
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"Failed attempting to set the MRRS\n");
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mrrs /= 2;
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}
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@ -1436,13 +1439,13 @@ static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
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if (!pci_is_pcie(dev))
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return 0;
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dev_info(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n",
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dev_dbg(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n",
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pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev));
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pcie_write_mps(dev, mps);
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pcie_write_mrrs(dev, mps);
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dev_info(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n",
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dev_dbg(&dev->dev, "Dev MPS %d MPSS %d MRRS %d\n",
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pcie_get_mps(dev), 128<<dev->pcie_mpss, pcie_get_readrq(dev));
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return 0;
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