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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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drm/i915: Add platform information to implemented workarounds
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Damien Lespiau
Daniel Vetter
parent
c77bf5659d
commit
ecdb4eb71b
@ -1198,9 +1198,9 @@ MODULE_LICENSE("GPL and additional rights");
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static void
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ilk_dummy_write(struct drm_i915_private *dev_priv)
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{
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/* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
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* chip from rc6 before touching it for real. MI_MODE is masked, hence
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* harmless to write 0 into. */
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/* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
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* the chip from rc6 before touching it for real. MI_MODE is masked,
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* hence harmless to write 0 into. */
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I915_WRITE_NOTRACE(MI_MODE, 0);
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}
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@ -3808,7 +3808,7 @@ static void ironlake_init_clock_gating(struct drm_device *dev)
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_3D_CHICKEN2_WM_READ_PIPELINED << 16 |
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_3D_CHICKEN2_WM_READ_PIPELINED);
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/* WaDisableRenderCachePipelinedFlush */
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/* WaDisableRenderCachePipelinedFlush:ilk */
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I915_WRITE(CACHE_MODE_0,
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_MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
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@ -3875,11 +3875,11 @@ static void gen6_init_clock_gating(struct drm_device *dev)
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I915_READ(ILK_DISPLAY_CHICKEN2) |
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ILK_ELPIN_409_SELECT);
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/* WaDisableHiZPlanesWhenMSAAEnabled */
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/* WaDisableHiZPlanesWhenMSAAEnabled:snb */
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I915_WRITE(_3D_CHICKEN,
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_MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
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/* WaSetupGtModeTdRowDispatch */
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/* WaSetupGtModeTdRowDispatch:snb */
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if (IS_SNB_GT1(dev))
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I915_WRITE(GEN6_GT_MODE,
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_MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
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@ -3906,8 +3906,8 @@ static void gen6_init_clock_gating(struct drm_device *dev)
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* According to the spec, bit 11 (RCCUNIT) must also be set,
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* but we didn't debug actual testcases to find it out.
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*
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* Also apply WaDisableVDSUnitClockGating and
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* WaDisableRCPBUnitClockGating.
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* Also apply WaDisableVDSUnitClockGating:snb and
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* WaDisableRCPBUnitClockGating:snb.
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*/
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I915_WRITE(GEN6_UCGCTL2,
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GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
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@ -3938,7 +3938,7 @@ static void gen6_init_clock_gating(struct drm_device *dev)
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ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
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ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
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/* WaMbcDriverBootEnable */
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/* WaMbcDriverBootEnable:snb */
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I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
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GEN6_MBCTL_ENABLE_BOOT_FETCH);
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@ -3968,7 +3968,6 @@ static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
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reg |= GEN7_FF_VS_SCHED_HW;
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reg |= GEN7_FF_DS_SCHED_HW;
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/* WaVSRefCountFullforceMissDisable */
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if (IS_HASWELL(dev_priv->dev))
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reg &= ~GEN7_FF_VS_REF_CNT_FFME;
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@ -3999,21 +3998,21 @@ static void haswell_init_clock_gating(struct drm_device *dev)
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I915_WRITE(WM1_LP_ILK, 0);
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/* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
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* This implements the WaDisableRCZUnitClockGating workaround.
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* This implements the WaDisableRCZUnitClockGating:hsw workaround.
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*/
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I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
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/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
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/* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
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I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
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GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
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/* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
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/* WaApplyL3ControlAndL3ChickenMode:hsw */
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I915_WRITE(GEN7_L3CNTLREG1,
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GEN7_WA_FOR_GEN7_L3_CONTROL);
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I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
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GEN7_WA_L3_CHICKEN_MODE);
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/* This is required by WaCatErrorRejectionIssue */
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/* This is required by WaCatErrorRejectionIssue:hsw */
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I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
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I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
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GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
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@ -4025,17 +4024,18 @@ static void haswell_init_clock_gating(struct drm_device *dev)
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intel_flush_display_plane(dev_priv, pipe);
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}
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/* WaVSRefCountFullforceMissDisable:hsw */
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gen7_setup_fixed_func_scheduler(dev_priv);
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/* WaDisable4x2SubspanOptimization */
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/* WaDisable4x2SubspanOptimization:hsw */
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I915_WRITE(CACHE_MODE_1,
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_MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
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/* WaMbcDriverBootEnable */
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/* WaMbcDriverBootEnable:hsw */
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I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
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GEN6_MBCTL_ENABLE_BOOT_FETCH);
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/* WaSwitchSolVfFArbitrationPriority */
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/* WaSwitchSolVfFArbitrationPriority:hsw */
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I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
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/* XXX: This is a workaround for early silicon revisions and should be
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@ -4062,16 +4062,16 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
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I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
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/* WaDisableEarlyCull */
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/* WaDisableEarlyCull:ivb */
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I915_WRITE(_3D_CHICKEN3,
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_MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
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/* WaDisableBackToBackFlipFix */
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/* WaDisableBackToBackFlipFix:ivb */
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I915_WRITE(IVB_CHICKEN3,
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CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
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CHICKEN3_DGMG_DONE_FIX_DISABLE);
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/* WaDisablePSDDualDispatchEnable */
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/* WaDisablePSDDualDispatchEnable:ivb */
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if (IS_IVB_GT1(dev))
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I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
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_MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
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@ -4079,11 +4079,11 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
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I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
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_MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
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/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
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/* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
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I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
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GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
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/* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
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/* WaApplyL3ControlAndL3ChickenMode:ivb */
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I915_WRITE(GEN7_L3CNTLREG1,
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GEN7_WA_FOR_GEN7_L3_CONTROL);
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I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
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@ -4096,7 +4096,7 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
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_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
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/* WaForceL3Serialization */
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/* WaForceL3Serialization:ivb */
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I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
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~L3SQ_URB_READ_CAM_MATCH_DISABLE);
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@ -4111,13 +4111,13 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
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* but we didn't debug actual testcases to find it out.
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*
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* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
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* This implements the WaDisableRCZUnitClockGating workaround.
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* This implements the WaDisableRCZUnitClockGating:ivb workaround.
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*/
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I915_WRITE(GEN6_UCGCTL2,
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GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
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GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
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/* This is required by WaCatErrorRejectionIssue */
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/* This is required by WaCatErrorRejectionIssue:ivb */
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I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
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I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
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GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
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@ -4129,13 +4129,14 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
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intel_flush_display_plane(dev_priv, pipe);
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}
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/* WaMbcDriverBootEnable */
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/* WaMbcDriverBootEnable:ivb */
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I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
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GEN6_MBCTL_ENABLE_BOOT_FETCH);
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/* WaVSRefCountFullforceMissDisable:ivb */
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gen7_setup_fixed_func_scheduler(dev_priv);
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/* WaDisable4x2SubspanOptimization */
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/* WaDisable4x2SubspanOptimization:ivb */
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I915_WRITE(CACHE_MODE_1,
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_MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
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@ -4161,46 +4162,46 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
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I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
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/* WaDisableEarlyCull */
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/* WaDisableEarlyCull:vlv */
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I915_WRITE(_3D_CHICKEN3,
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_MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
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/* WaDisableBackToBackFlipFix */
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/* WaDisableBackToBackFlipFix:vlv */
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I915_WRITE(IVB_CHICKEN3,
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CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
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CHICKEN3_DGMG_DONE_FIX_DISABLE);
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/* WaDisablePSDDualDispatchEnable */
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/* WaDisablePSDDualDispatchEnable:vlv */
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I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
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_MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
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GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
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/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
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/* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
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I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
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GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
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/* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
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/* WaApplyL3ControlAndL3ChickenMode:vlv */
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I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
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I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
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/* WaForceL3Serialization */
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/* WaForceL3Serialization:vlv */
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I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
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~L3SQ_URB_READ_CAM_MATCH_DISABLE);
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/* WaDisableDopClockGating */
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/* WaDisableDopClockGating:vlv */
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I915_WRITE(GEN7_ROW_CHICKEN2,
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_MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
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/* WaForceL3Serialization */
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/* WaForceL3Serialization:vlv */
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I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
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~L3SQ_URB_READ_CAM_MATCH_DISABLE);
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/* This is required by WaCatErrorRejectionIssue */
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/* This is required by WaCatErrorRejectionIssue:vlv */
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I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
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I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
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GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
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/* WaMbcDriverBootEnable */
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/* WaMbcDriverBootEnable:vlv */
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I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
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GEN6_MBCTL_ENABLE_BOOT_FETCH);
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@ -4216,10 +4217,10 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
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* but we didn't debug actual testcases to find it out.
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*
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* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
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* This implements the WaDisableRCZUnitClockGating workaround.
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* This implements the WaDisableRCZUnitClockGating:vlv workaround.
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*
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* Also apply WaDisableVDSUnitClockGating and
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* WaDisableRCPBUnitClockGating.
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* Also apply WaDisableVDSUnitClockGating:vlv and
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* WaDisableRCPBUnitClockGating:vlv.
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*/
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I915_WRITE(GEN6_UCGCTL2,
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GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
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@ -4241,7 +4242,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
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_MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
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/*
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* WaDisableVLVClockGating_VBIIssue
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* WaDisableVLVClockGating_VBIIssue:vlv
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* Disable clock gating on th GCFG unit to prevent a delay
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* in the reporting of vblank events.
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*/
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