mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 16:26:39 +07:00
drm/nouveau/msvld: separate from bsp
Switch to NVIDIA's name for the device. The namespace of NVKM is being changed to nvkm_ instead of nouveau_, which will be used for the DRM part of the driver. This is being done in order to make it very clear as to what part of the driver a given symbol belongs to, and as a minor step towards splitting the DRM driver out to be able to stand on its own (for virt). Because there's already a large amount of churn here anyway, this is as good a time as any to also switch to NVIDIA's device and chipset naming to ease collaboration with them. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
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5ce3bf3c72
commit
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@ -134,6 +134,7 @@ struct nv_device_v0 {
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#define NV_DEVICE_V0_DISABLE_VIC 0x0000020000000000ULL
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#define NV_DEVICE_V0_DISABLE_VENC 0x0000040000000000ULL
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#define NV_DEVICE_V0_DISABLE_COPY2 0x0000080000000000ULL
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#define NV_DEVICE_V0_DISABLE_MSVLD 0x0000100000000000ULL
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__u64 disable; /* disable particular subsystems */
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__u64 debug0; /* as above, but *internal* ids, and *NOT* ABI */
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};
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@ -348,7 +349,7 @@ struct kepler_channel_gpfifo_a_v0 {
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#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR 0x01
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#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_VP 0x02
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#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_PPP 0x04
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#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_BSP 0x08
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#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD 0x08
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#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0 0x10
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#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1 0x20
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#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_ENC 0x40
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@ -59,6 +59,7 @@ enum nv_subdev_type {
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NVDEV_ENGINE_VENC,
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NVDEV_ENGINE_DISP,
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NVDEV_ENGINE_PERFMON,
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NVDEV_ENGINE_MSVLD,
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NVDEV_SUBDEV_NR,
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};
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@ -1,9 +1,4 @@
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#ifndef __NOUVEAU_BSP_H__
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#define __NOUVEAU_BSP_H__
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extern struct nouveau_oclass nv84_bsp_oclass;
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extern struct nouveau_oclass nv98_bsp_oclass;
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extern struct nouveau_oclass nvc0_bsp_oclass;
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extern struct nouveau_oclass nve0_bsp_oclass;
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#endif
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6
drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h
Normal file
6
drivers/gpu/drm/nouveau/include/nvkm/engine/msvld.h
Normal file
@ -0,0 +1,6 @@
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#ifndef __NVKM_MSVLD_H__
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#define __NVKM_MSVLD_H__
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extern struct nouveau_oclass nv98_msvld_oclass;
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extern struct nouveau_oclass nvc0_msvld_oclass;
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extern struct nouveau_oclass nve0_msvld_oclass;
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#endif
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@ -10,6 +10,7 @@ include $(src)/nvkm/engine/dmaobj/Kbuild
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include $(src)/nvkm/engine/fifo/Kbuild
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include $(src)/nvkm/engine/graph/Kbuild
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include $(src)/nvkm/engine/mpeg/Kbuild
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include $(src)/nvkm/engine/msvld/Kbuild
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include $(src)/nvkm/engine/perfmon/Kbuild
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include $(src)/nvkm/engine/ppp/Kbuild
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include $(src)/nvkm/engine/software/Kbuild
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@ -1,4 +1 @@
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nvkm-y += nvkm/engine/bsp/nv84.o
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nvkm-y += nvkm/engine/bsp/nv98.o
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nvkm-y += nvkm/engine/bsp/nvc0.o
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nvkm-y += nvkm/engine/bsp/nve0.o
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@ -241,6 +241,7 @@ static const u64 disable_map[] = {
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[NVDEV_ENGINE_VIC] = NV_DEVICE_V0_DISABLE_VIC,
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[NVDEV_ENGINE_VENC] = NV_DEVICE_V0_DISABLE_VENC,
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[NVDEV_ENGINE_DISP] = NV_DEVICE_V0_DISABLE_DISP,
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[NVDEV_ENGINE_MSVLD] = NV_DEVICE_V0_DISABLE_MSVLD,
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[NVDEV_SUBDEV_NR] = 0,
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};
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@ -50,6 +50,7 @@
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#include <engine/disp.h>
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#include <engine/copy.h>
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#include <engine/bsp.h>
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#include <engine/msvld.h>
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#include <engine/vp.h>
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#include <engine/ppp.h>
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#include <engine/perfmon.h>
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@ -93,7 +94,7 @@ gm100_identify(struct nouveau_device *device)
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#endif
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device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
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#if 0
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device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
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device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
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#endif
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@ -136,7 +137,7 @@ gm100_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_COPY0 ] = &gm204_copy0_oclass;
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device->oclass[NVDEV_ENGINE_COPY1 ] = &gm204_copy1_oclass;
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device->oclass[NVDEV_ENGINE_COPY2 ] = &gm204_copy2_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
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device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
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#endif
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@ -49,6 +49,7 @@
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#include <engine/vp.h>
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#include <engine/crypt.h>
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#include <engine/bsp.h>
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#include <engine/msvld.h>
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#include <engine/ppp.h>
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#include <engine/copy.h>
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#include <engine/disp.h>
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@ -253,7 +254,7 @@ nv50_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
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device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
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device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
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device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
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device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
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@ -311,7 +312,7 @@ nv50_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
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device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
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device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
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device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
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device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
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@ -340,7 +341,7 @@ nv50_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
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device->oclass[NVDEV_ENGINE_CRYPT ] = &nv98_crypt_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
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device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
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device->oclass[NVDEV_ENGINE_DISP ] = nv94_disp_oclass;
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device->oclass[NVDEV_ENGINE_PERFMON] = nv84_perfmon_oclass;
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@ -370,7 +371,7 @@ nv50_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
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device->oclass[NVDEV_ENGINE_MPEG ] = &nv84_mpeg_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
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device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
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device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
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@ -400,7 +401,7 @@ nv50_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
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device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
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device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
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@ -430,7 +431,7 @@ nv50_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
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device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
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device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
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@ -460,7 +461,7 @@ nv50_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_SW ] = nv50_software_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = &nv50_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nv98_vp_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nv98_bsp_oclass;
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device->oclass[NVDEV_ENGINE_MSVLD ] = &nv98_msvld_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nv98_ppp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nva3_copy_oclass;
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device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
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@ -49,6 +49,7 @@
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#include <engine/graph.h>
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#include <engine/vp.h>
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#include <engine/bsp.h>
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#include <engine/msvld.h>
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#include <engine/ppp.h>
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#include <engine/copy.h>
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#include <engine/disp.h>
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@ -84,7 +85,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = nvc0_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
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device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
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device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
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@ -117,7 +118,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
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device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
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device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
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@ -150,7 +151,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
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device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
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device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
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@ -182,7 +183,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
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device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
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device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
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@ -215,7 +216,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = nvc4_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
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device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
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device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
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@ -247,7 +248,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = nvc1_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
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device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
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device->oclass[NVDEV_ENGINE_DISP ] = nva3_disp_oclass;
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@ -279,7 +280,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = nvc8_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
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device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
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device->oclass[NVDEV_ENGINE_COPY1 ] = &nvc0_copy1_oclass;
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@ -312,7 +313,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = nvd9_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
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device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
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device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass;
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@ -342,7 +343,7 @@ nvc0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_SW ] = nvc0_software_oclass;
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device->oclass[NVDEV_ENGINE_GR ] = nvd7_graph_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nvc0_vp_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nvc0_bsp_oclass;
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device->oclass[NVDEV_ENGINE_MSVLD ] = &nvc0_msvld_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nvc0_copy0_oclass;
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device->oclass[NVDEV_ENGINE_DISP ] = nvd0_disp_oclass;
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@ -50,6 +50,7 @@
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#include <engine/disp.h>
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#include <engine/copy.h>
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#include <engine/bsp.h>
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#include <engine/msvld.h>
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#include <engine/vp.h>
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#include <engine/ppp.h>
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#include <engine/perfmon.h>
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@ -87,7 +88,7 @@ nve0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
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device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
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device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
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device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
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device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
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device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
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device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
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device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
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@ -121,7 +122,7 @@ nve0_identify(struct nouveau_device *device)
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device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
|
||||
device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
|
||||
device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
|
||||
device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
|
||||
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
|
||||
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
|
||||
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
|
||||
device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
|
||||
@ -155,7 +156,7 @@ nve0_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
|
||||
device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
|
||||
device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
|
||||
device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
|
||||
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
|
||||
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
|
||||
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
|
||||
device->oclass[NVDEV_ENGINE_PERFMON] = &nve0_perfmon_oclass;
|
||||
@ -211,7 +212,7 @@ nve0_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
|
||||
device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
|
||||
device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
|
||||
device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
|
||||
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
|
||||
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
|
||||
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
|
||||
device->oclass[NVDEV_ENGINE_PERFMON] = &nvf0_perfmon_oclass;
|
||||
@ -245,7 +246,7 @@ nve0_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
|
||||
device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
|
||||
device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
|
||||
device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
|
||||
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
|
||||
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
|
||||
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
|
||||
device->oclass[NVDEV_ENGINE_PERFMON] = &nvf0_perfmon_oclass;
|
||||
@ -279,7 +280,7 @@ nve0_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
|
||||
device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
|
||||
device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
|
||||
device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
|
||||
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
|
||||
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
|
||||
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
|
||||
break;
|
||||
@ -312,7 +313,7 @@ nve0_identify(struct nouveau_device *device)
|
||||
device->oclass[NVDEV_ENGINE_COPY0 ] = &nve0_copy0_oclass;
|
||||
device->oclass[NVDEV_ENGINE_COPY1 ] = &nve0_copy1_oclass;
|
||||
device->oclass[NVDEV_ENGINE_COPY2 ] = &nve0_copy2_oclass;
|
||||
device->oclass[NVDEV_ENGINE_BSP ] = &nve0_bsp_oclass;
|
||||
device->oclass[NVDEV_ENGINE_MSVLD ] = &nve0_msvld_oclass;
|
||||
device->oclass[NVDEV_ENGINE_VP ] = &nve0_vp_oclass;
|
||||
device->oclass[NVDEV_ENGINE_PPP ] = &nvc0_ppp_oclass;
|
||||
break;
|
||||
|
@ -60,7 +60,8 @@ nv84_fifo_context_attach(struct nouveau_object *parent,
|
||||
case NVDEV_ENGINE_VP : addr = 0x0040; break;
|
||||
case NVDEV_ENGINE_PPP :
|
||||
case NVDEV_ENGINE_MPEG : addr = 0x0060; break;
|
||||
case NVDEV_ENGINE_BSP : addr = 0x0080; break;
|
||||
case NVDEV_ENGINE_BSP :
|
||||
case NVDEV_ENGINE_MSVLD: addr = 0x0080; break;
|
||||
case NVDEV_ENGINE_CRYPT: addr = 0x00a0; break;
|
||||
case NVDEV_ENGINE_COPY0: addr = 0x00c0; break;
|
||||
default:
|
||||
@ -96,7 +97,8 @@ nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend,
|
||||
case NVDEV_ENGINE_VP : engn = 3; addr = 0x0040; break;
|
||||
case NVDEV_ENGINE_PPP :
|
||||
case NVDEV_ENGINE_MPEG : engn = 1; addr = 0x0060; break;
|
||||
case NVDEV_ENGINE_BSP : engn = 5; addr = 0x0080; break;
|
||||
case NVDEV_ENGINE_BSP :
|
||||
case NVDEV_ENGINE_MSVLD: engn = 5; addr = 0x0080; break;
|
||||
case NVDEV_ENGINE_CRYPT: engn = 4; addr = 0x00a0; break;
|
||||
case NVDEV_ENGINE_COPY0: engn = 2; addr = 0x00c0; break;
|
||||
default:
|
||||
@ -147,7 +149,8 @@ nv84_fifo_object_attach(struct nouveau_object *parent,
|
||||
case NVDEV_ENGINE_VP : context |= 0x00400000; break;
|
||||
case NVDEV_ENGINE_CRYPT :
|
||||
case NVDEV_ENGINE_VIC : context |= 0x00500000; break;
|
||||
case NVDEV_ENGINE_BSP : context |= 0x00600000; break;
|
||||
case NVDEV_ENGINE_BSP :
|
||||
case NVDEV_ENGINE_MSVLD : context |= 0x00600000; break;
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
@ -187,6 +190,7 @@ nv84_fifo_chan_ctor_dma(struct nouveau_object *parent,
|
||||
(1ULL << NVDEV_ENGINE_VP) |
|
||||
(1ULL << NVDEV_ENGINE_CRYPT) |
|
||||
(1ULL << NVDEV_ENGINE_BSP) |
|
||||
(1ULL << NVDEV_ENGINE_MSVLD) |
|
||||
(1ULL << NVDEV_ENGINE_PPP) |
|
||||
(1ULL << NVDEV_ENGINE_COPY0) |
|
||||
(1ULL << NVDEV_ENGINE_VIC), &chan);
|
||||
@ -260,6 +264,7 @@ nv84_fifo_chan_ctor_ind(struct nouveau_object *parent,
|
||||
(1ULL << NVDEV_ENGINE_VP) |
|
||||
(1ULL << NVDEV_ENGINE_CRYPT) |
|
||||
(1ULL << NVDEV_ENGINE_BSP) |
|
||||
(1ULL << NVDEV_ENGINE_MSVLD) |
|
||||
(1ULL << NVDEV_ENGINE_PPP) |
|
||||
(1ULL << NVDEV_ENGINE_COPY0) |
|
||||
(1ULL << NVDEV_ENGINE_VIC), &chan);
|
||||
|
@ -124,7 +124,7 @@ nvc0_fifo_context_attach(struct nouveau_object *parent,
|
||||
case NVDEV_ENGINE_GR : addr = 0x0210; break;
|
||||
case NVDEV_ENGINE_COPY0: addr = 0x0230; break;
|
||||
case NVDEV_ENGINE_COPY1: addr = 0x0240; break;
|
||||
case NVDEV_ENGINE_BSP : addr = 0x0270; break;
|
||||
case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
|
||||
case NVDEV_ENGINE_VP : addr = 0x0250; break;
|
||||
case NVDEV_ENGINE_PPP : addr = 0x0260; break;
|
||||
default:
|
||||
@ -161,7 +161,7 @@ nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
|
||||
case NVDEV_ENGINE_GR : addr = 0x0210; break;
|
||||
case NVDEV_ENGINE_COPY0: addr = 0x0230; break;
|
||||
case NVDEV_ENGINE_COPY1: addr = 0x0240; break;
|
||||
case NVDEV_ENGINE_BSP : addr = 0x0270; break;
|
||||
case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
|
||||
case NVDEV_ENGINE_VP : addr = 0x0250; break;
|
||||
case NVDEV_ENGINE_PPP : addr = 0x0260; break;
|
||||
default:
|
||||
@ -214,7 +214,7 @@ nvc0_fifo_chan_ctor(struct nouveau_object *parent,
|
||||
(1ULL << NVDEV_ENGINE_GR) |
|
||||
(1ULL << NVDEV_ENGINE_COPY0) |
|
||||
(1ULL << NVDEV_ENGINE_COPY1) |
|
||||
(1ULL << NVDEV_ENGINE_BSP) |
|
||||
(1ULL << NVDEV_ENGINE_MSVLD) |
|
||||
(1ULL << NVDEV_ENGINE_VP) |
|
||||
(1ULL << NVDEV_ENGINE_PPP), &chan);
|
||||
*pobject = nv_object(chan);
|
||||
@ -382,7 +382,7 @@ nvc0_fifo_engidx(struct nvc0_fifo_priv *priv, u32 engn)
|
||||
{
|
||||
switch (engn) {
|
||||
case NVDEV_ENGINE_GR : engn = 0; break;
|
||||
case NVDEV_ENGINE_BSP : engn = 1; break;
|
||||
case NVDEV_ENGINE_MSVLD: engn = 1; break;
|
||||
case NVDEV_ENGINE_PPP : engn = 2; break;
|
||||
case NVDEV_ENGINE_VP : engn = 3; break;
|
||||
case NVDEV_ENGINE_COPY0: engn = 4; break;
|
||||
@ -399,7 +399,7 @@ nvc0_fifo_engine(struct nvc0_fifo_priv *priv, u32 engn)
|
||||
{
|
||||
switch (engn) {
|
||||
case 0: engn = NVDEV_ENGINE_GR; break;
|
||||
case 1: engn = NVDEV_ENGINE_BSP; break;
|
||||
case 1: engn = NVDEV_ENGINE_MSVLD; break;
|
||||
case 2: engn = NVDEV_ENGINE_PPP; break;
|
||||
case 3: engn = NVDEV_ENGINE_VP; break;
|
||||
case 4: engn = NVDEV_ENGINE_COPY0; break;
|
||||
@ -548,7 +548,7 @@ nvc0_fifo_fault_engine[] = {
|
||||
{ 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR },
|
||||
{ 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM },
|
||||
{ 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO },
|
||||
{ 0x10, "PBSP", NULL, NVDEV_ENGINE_BSP },
|
||||
{ 0x10, "PMSVLD", NULL, NVDEV_ENGINE_MSVLD },
|
||||
{ 0x11, "PPPP", NULL, NVDEV_ENGINE_PPP },
|
||||
{ 0x13, "PCOUNTER" },
|
||||
{ 0x14, "PVP", NULL, NVDEV_ENGINE_VP },
|
||||
@ -583,7 +583,7 @@ nvc0_fifo_fault_hubclient[] = {
|
||||
{ 0x08, "BAR_WRITE" },
|
||||
{ 0x0b, "PVP" },
|
||||
{ 0x0c, "PPPP" },
|
||||
{ 0x0d, "PBSP" },
|
||||
{ 0x0d, "PMSVLD" },
|
||||
{ 0x11, "PCOUNTER" },
|
||||
{ 0x12, "PDAEMON" },
|
||||
{ 0x14, "CCACHE" },
|
||||
@ -941,7 +941,7 @@ nvc0_fifo_init(struct nouveau_object *object)
|
||||
nv_wr32(priv, 0x002208, ~(1 << 0)); /* PGRAPH */
|
||||
nv_wr32(priv, 0x00220c, ~(1 << 1)); /* PVP */
|
||||
nv_wr32(priv, 0x002210, ~(1 << 1)); /* PPP */
|
||||
nv_wr32(priv, 0x002214, ~(1 << 1)); /* PBSP */
|
||||
nv_wr32(priv, 0x002214, ~(1 << 1)); /* PMSVLD */
|
||||
nv_wr32(priv, 0x002218, ~(1 << 2)); /* PCE0 */
|
||||
nv_wr32(priv, 0x00221c, ~(1 << 1)); /* PCE1 */
|
||||
}
|
||||
|
@ -50,7 +50,7 @@ static const struct {
|
||||
(1ULL << NVDEV_ENGINE_COPY2)),
|
||||
_(NVDEV_ENGINE_VP , 0),
|
||||
_(NVDEV_ENGINE_PPP , 0),
|
||||
_(NVDEV_ENGINE_BSP , 0),
|
||||
_(NVDEV_ENGINE_MSVLD , 0),
|
||||
_(NVDEV_ENGINE_COPY0 , 0),
|
||||
_(NVDEV_ENGINE_COPY1 , 0),
|
||||
_(NVDEV_ENGINE_VENC , 0),
|
||||
@ -149,7 +149,7 @@ nve0_fifo_context_attach(struct nouveau_object *parent,
|
||||
nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12;
|
||||
return 0;
|
||||
case NVDEV_ENGINE_GR : addr = 0x0210; break;
|
||||
case NVDEV_ENGINE_BSP : addr = 0x0270; break;
|
||||
case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
|
||||
case NVDEV_ENGINE_VP : addr = 0x0250; break;
|
||||
case NVDEV_ENGINE_PPP : addr = 0x0260; break;
|
||||
default:
|
||||
@ -187,7 +187,7 @@ nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
|
||||
case NVDEV_ENGINE_COPY1:
|
||||
case NVDEV_ENGINE_COPY2: addr = 0x0000; break;
|
||||
case NVDEV_ENGINE_GR : addr = 0x0210; break;
|
||||
case NVDEV_ENGINE_BSP : addr = 0x0270; break;
|
||||
case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
|
||||
case NVDEV_ENGINE_VP : addr = 0x0250; break;
|
||||
case NVDEV_ENGINE_PPP : addr = 0x0260; break;
|
||||
default:
|
||||
@ -416,7 +416,7 @@ nve0_fifo_engidx(struct nve0_fifo_priv *priv, u32 engn)
|
||||
switch (engn) {
|
||||
case NVDEV_ENGINE_GR :
|
||||
case NVDEV_ENGINE_COPY2: engn = 0; break;
|
||||
case NVDEV_ENGINE_BSP : engn = 1; break;
|
||||
case NVDEV_ENGINE_MSVLD: engn = 1; break;
|
||||
case NVDEV_ENGINE_PPP : engn = 2; break;
|
||||
case NVDEV_ENGINE_VP : engn = 3; break;
|
||||
case NVDEV_ENGINE_COPY0: engn = 4; break;
|
||||
@ -619,7 +619,7 @@ nve0_fifo_fault_engine[] = {
|
||||
{ 0x07, "PBDMA0", NULL, NVDEV_ENGINE_FIFO },
|
||||
{ 0x08, "PBDMA1", NULL, NVDEV_ENGINE_FIFO },
|
||||
{ 0x09, "PBDMA2", NULL, NVDEV_ENGINE_FIFO },
|
||||
{ 0x10, "MSVLD", NULL, NVDEV_ENGINE_BSP },
|
||||
{ 0x10, "MSVLD", NULL, NVDEV_ENGINE_MSVLD },
|
||||
{ 0x11, "MSPPP", NULL, NVDEV_ENGINE_PPP },
|
||||
{ 0x13, "PERF" },
|
||||
{ 0x14, "MSPDEC", NULL, NVDEV_ENGINE_VP },
|
||||
|
3
drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild
Normal file
3
drivers/gpu/drm/nouveau/nvkm/engine/msvld/Kbuild
Normal file
@ -0,0 +1,3 @@
|
||||
nvkm-y += nvkm/engine/msvld/nv98.o
|
||||
nvkm-y += nvkm/engine/msvld/nvc0.o
|
||||
nvkm-y += nvkm/engine/msvld/nve0.o
|
@ -23,18 +23,18 @@
|
||||
*/
|
||||
|
||||
#include <engine/falcon.h>
|
||||
#include <engine/bsp.h>
|
||||
#include <engine/msvld.h>
|
||||
|
||||
struct nv98_bsp_priv {
|
||||
struct nv98_msvld_priv {
|
||||
struct nouveau_falcon base;
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* BSP object classes
|
||||
* MSVLD object classes
|
||||
******************************************************************************/
|
||||
|
||||
static struct nouveau_oclass
|
||||
nv98_bsp_sclass[] = {
|
||||
nv98_msvld_sclass[] = {
|
||||
{ 0x88b1, &nouveau_object_ofuncs },
|
||||
{ 0x85b1, &nouveau_object_ofuncs },
|
||||
{ 0x86b1, &nouveau_object_ofuncs },
|
||||
@ -42,12 +42,12 @@ nv98_bsp_sclass[] = {
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* PBSP context
|
||||
* PMSVLD context
|
||||
******************************************************************************/
|
||||
|
||||
static struct nouveau_oclass
|
||||
nv98_bsp_cclass = {
|
||||
.handle = NV_ENGCTX(BSP, 0x98),
|
||||
nv98_msvld_cclass = {
|
||||
.handle = NV_ENGCTX(MSVLD, 0x98),
|
||||
.ofuncs = &(struct nouveau_ofuncs) {
|
||||
.ctor = _nouveau_falcon_context_ctor,
|
||||
.dtor = _nouveau_falcon_context_dtor,
|
||||
@ -59,13 +59,13 @@ nv98_bsp_cclass = {
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* PBSP engine/subdev functions
|
||||
* PMSVLD engine/subdev functions
|
||||
******************************************************************************/
|
||||
|
||||
static int
|
||||
nv98_bsp_init(struct nouveau_object *object)
|
||||
nv98_msvld_init(struct nouveau_object *object)
|
||||
{
|
||||
struct nv98_bsp_priv *priv = (void *)object;
|
||||
struct nv98_msvld_priv *priv = (void *)object;
|
||||
int ret;
|
||||
|
||||
ret = nouveau_falcon_init(&priv->base);
|
||||
@ -78,32 +78,32 @@ nv98_bsp_init(struct nouveau_object *object)
|
||||
}
|
||||
|
||||
static int
|
||||
nv98_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
|
||||
nv98_msvld_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
|
||||
struct nouveau_oclass *oclass, void *data, u32 size,
|
||||
struct nouveau_object **pobject)
|
||||
{
|
||||
struct nv98_bsp_priv *priv;
|
||||
struct nv98_msvld_priv *priv;
|
||||
int ret;
|
||||
|
||||
ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true,
|
||||
"PBSP", "bsp", &priv);
|
||||
"PMSVLD", "msvld", &priv);
|
||||
*pobject = nv_object(priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_subdev(priv)->unit = 0x04008000;
|
||||
nv_engine(priv)->cclass = &nv98_bsp_cclass;
|
||||
nv_engine(priv)->sclass = nv98_bsp_sclass;
|
||||
nv_engine(priv)->cclass = &nv98_msvld_cclass;
|
||||
nv_engine(priv)->sclass = nv98_msvld_sclass;
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct nouveau_oclass
|
||||
nv98_bsp_oclass = {
|
||||
.handle = NV_ENGINE(BSP, 0x98),
|
||||
nv98_msvld_oclass = {
|
||||
.handle = NV_ENGINE(MSVLD, 0x98),
|
||||
.ofuncs = &(struct nouveau_ofuncs) {
|
||||
.ctor = nv98_bsp_ctor,
|
||||
.ctor = nv98_msvld_ctor,
|
||||
.dtor = _nouveau_falcon_dtor,
|
||||
.init = nv98_bsp_init,
|
||||
.init = nv98_msvld_init,
|
||||
.fini = _nouveau_falcon_fini,
|
||||
.rd32 = _nouveau_falcon_rd32,
|
||||
.wr32 = _nouveau_falcon_wr32,
|
@ -23,29 +23,29 @@
|
||||
*/
|
||||
|
||||
#include <engine/falcon.h>
|
||||
#include <engine/bsp.h>
|
||||
#include <engine/msvld.h>
|
||||
|
||||
struct nvc0_bsp_priv {
|
||||
struct nvc0_msvld_priv {
|
||||
struct nouveau_falcon base;
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* BSP object classes
|
||||
* MSVLD object classes
|
||||
******************************************************************************/
|
||||
|
||||
static struct nouveau_oclass
|
||||
nvc0_bsp_sclass[] = {
|
||||
nvc0_msvld_sclass[] = {
|
||||
{ 0x90b1, &nouveau_object_ofuncs },
|
||||
{},
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* PBSP context
|
||||
* PMSVLD context
|
||||
******************************************************************************/
|
||||
|
||||
static struct nouveau_oclass
|
||||
nvc0_bsp_cclass = {
|
||||
.handle = NV_ENGCTX(BSP, 0xc0),
|
||||
nvc0_msvld_cclass = {
|
||||
.handle = NV_ENGCTX(MSVLD, 0xc0),
|
||||
.ofuncs = &(struct nouveau_ofuncs) {
|
||||
.ctor = _nouveau_falcon_context_ctor,
|
||||
.dtor = _nouveau_falcon_context_dtor,
|
||||
@ -57,13 +57,13 @@ nvc0_bsp_cclass = {
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* PBSP engine/subdev functions
|
||||
* PMSVLD engine/subdev functions
|
||||
******************************************************************************/
|
||||
|
||||
static int
|
||||
nvc0_bsp_init(struct nouveau_object *object)
|
||||
nvc0_msvld_init(struct nouveau_object *object)
|
||||
{
|
||||
struct nvc0_bsp_priv *priv = (void *)object;
|
||||
struct nvc0_msvld_priv *priv = (void *)object;
|
||||
int ret;
|
||||
|
||||
ret = nouveau_falcon_init(&priv->base);
|
||||
@ -76,33 +76,33 @@ nvc0_bsp_init(struct nouveau_object *object)
|
||||
}
|
||||
|
||||
static int
|
||||
nvc0_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
|
||||
nvc0_msvld_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
|
||||
struct nouveau_oclass *oclass, void *data, u32 size,
|
||||
struct nouveau_object **pobject)
|
||||
{
|
||||
struct nvc0_bsp_priv *priv;
|
||||
struct nvc0_msvld_priv *priv;
|
||||
int ret;
|
||||
|
||||
ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true,
|
||||
"PBSP", "bsp", &priv);
|
||||
"PMSVLD", "msvld", &priv);
|
||||
*pobject = nv_object(priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_subdev(priv)->unit = 0x00008000;
|
||||
nv_subdev(priv)->intr = nouveau_falcon_intr;
|
||||
nv_engine(priv)->cclass = &nvc0_bsp_cclass;
|
||||
nv_engine(priv)->sclass = nvc0_bsp_sclass;
|
||||
nv_engine(priv)->cclass = &nvc0_msvld_cclass;
|
||||
nv_engine(priv)->sclass = nvc0_msvld_sclass;
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct nouveau_oclass
|
||||
nvc0_bsp_oclass = {
|
||||
.handle = NV_ENGINE(BSP, 0xc0),
|
||||
nvc0_msvld_oclass = {
|
||||
.handle = NV_ENGINE(MSVLD, 0xc0),
|
||||
.ofuncs = &(struct nouveau_ofuncs) {
|
||||
.ctor = nvc0_bsp_ctor,
|
||||
.ctor = nvc0_msvld_ctor,
|
||||
.dtor = _nouveau_falcon_dtor,
|
||||
.init = nvc0_bsp_init,
|
||||
.init = nvc0_msvld_init,
|
||||
.fini = _nouveau_falcon_fini,
|
||||
.rd32 = _nouveau_falcon_rd32,
|
||||
.wr32 = _nouveau_falcon_wr32,
|
@ -23,29 +23,29 @@
|
||||
*/
|
||||
|
||||
#include <engine/falcon.h>
|
||||
#include <engine/bsp.h>
|
||||
#include <engine/msvld.h>
|
||||
|
||||
struct nve0_bsp_priv {
|
||||
struct nve0_msvld_priv {
|
||||
struct nouveau_falcon base;
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* BSP object classes
|
||||
* MSVLD object classes
|
||||
******************************************************************************/
|
||||
|
||||
static struct nouveau_oclass
|
||||
nve0_bsp_sclass[] = {
|
||||
nve0_msvld_sclass[] = {
|
||||
{ 0x95b1, &nouveau_object_ofuncs },
|
||||
{},
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* PBSP context
|
||||
* PMSVLD context
|
||||
******************************************************************************/
|
||||
|
||||
static struct nouveau_oclass
|
||||
nve0_bsp_cclass = {
|
||||
.handle = NV_ENGCTX(BSP, 0xe0),
|
||||
nve0_msvld_cclass = {
|
||||
.handle = NV_ENGCTX(MSVLD, 0xe0),
|
||||
.ofuncs = &(struct nouveau_ofuncs) {
|
||||
.ctor = _nouveau_falcon_context_ctor,
|
||||
.dtor = _nouveau_falcon_context_dtor,
|
||||
@ -57,13 +57,13 @@ nve0_bsp_cclass = {
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* PBSP engine/subdev functions
|
||||
* PMSVLD engine/subdev functions
|
||||
******************************************************************************/
|
||||
|
||||
static int
|
||||
nve0_bsp_init(struct nouveau_object *object)
|
||||
nve0_msvld_init(struct nouveau_object *object)
|
||||
{
|
||||
struct nve0_bsp_priv *priv = (void *)object;
|
||||
struct nve0_msvld_priv *priv = (void *)object;
|
||||
int ret;
|
||||
|
||||
ret = nouveau_falcon_init(&priv->base);
|
||||
@ -76,33 +76,33 @@ nve0_bsp_init(struct nouveau_object *object)
|
||||
}
|
||||
|
||||
static int
|
||||
nve0_bsp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
|
||||
nve0_msvld_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
|
||||
struct nouveau_oclass *oclass, void *data, u32 size,
|
||||
struct nouveau_object **pobject)
|
||||
{
|
||||
struct nve0_bsp_priv *priv;
|
||||
struct nve0_msvld_priv *priv;
|
||||
int ret;
|
||||
|
||||
ret = nouveau_falcon_create(parent, engine, oclass, 0x084000, true,
|
||||
"PBSP", "bsp", &priv);
|
||||
"PMSVLD", "msvld", &priv);
|
||||
*pobject = nv_object(priv);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_subdev(priv)->unit = 0x00008000;
|
||||
nv_subdev(priv)->intr = nouveau_falcon_intr;
|
||||
nv_engine(priv)->cclass = &nve0_bsp_cclass;
|
||||
nv_engine(priv)->sclass = nve0_bsp_sclass;
|
||||
nv_engine(priv)->cclass = &nve0_msvld_cclass;
|
||||
nv_engine(priv)->sclass = nve0_msvld_sclass;
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct nouveau_oclass
|
||||
nve0_bsp_oclass = {
|
||||
.handle = NV_ENGINE(BSP, 0xe0),
|
||||
nve0_msvld_oclass = {
|
||||
.handle = NV_ENGINE(MSVLD, 0xe0),
|
||||
.ofuncs = &(struct nouveau_ofuncs) {
|
||||
.ctor = nve0_bsp_ctor,
|
||||
.ctor = nve0_msvld_ctor,
|
||||
.dtor = _nouveau_falcon_dtor,
|
||||
.init = nve0_bsp_init,
|
||||
.init = nve0_msvld_init,
|
||||
.fini = _nouveau_falcon_fini,
|
||||
.rd32 = _nouveau_falcon_rd32,
|
||||
.wr32 = _nouveau_falcon_wr32,
|
@ -34,14 +34,14 @@ nv98_devinit_disable(struct nouveau_devinit *devinit)
|
||||
|
||||
if (!(r001540 & 0x40000000)) {
|
||||
disable |= (1ULL << NVDEV_ENGINE_VP);
|
||||
disable |= (1ULL << NVDEV_ENGINE_BSP);
|
||||
disable |= (1ULL << NVDEV_ENGINE_MSVLD);
|
||||
disable |= (1ULL << NVDEV_ENGINE_PPP);
|
||||
}
|
||||
|
||||
if (!(r00154c & 0x00000004))
|
||||
disable |= (1ULL << NVDEV_ENGINE_DISP);
|
||||
if (!(r00154c & 0x00000020))
|
||||
disable |= (1ULL << NVDEV_ENGINE_BSP);
|
||||
disable |= (1ULL << NVDEV_ENGINE_MSVLD);
|
||||
if (!(r00154c & 0x00000040))
|
||||
disable |= (1ULL << NVDEV_ENGINE_CRYPT);
|
||||
|
||||
|
@ -74,7 +74,7 @@ nva3_devinit_disable(struct nouveau_devinit *devinit)
|
||||
if (!(r00154c & 0x00000004))
|
||||
disable |= (1ULL << NVDEV_ENGINE_DISP);
|
||||
if (!(r00154c & 0x00000020))
|
||||
disable |= (1ULL << NVDEV_ENGINE_BSP);
|
||||
disable |= (1ULL << NVDEV_ENGINE_MSVLD);
|
||||
if (!(r00154c & 0x00000200))
|
||||
disable |= (1ULL << NVDEV_ENGINE_COPY0);
|
||||
|
||||
|
@ -40,7 +40,7 @@ nvaf_devinit_disable(struct nouveau_devinit *devinit)
|
||||
if (!(r00154c & 0x00000004))
|
||||
disable |= (1ULL << NVDEV_ENGINE_DISP);
|
||||
if (!(r00154c & 0x00000020))
|
||||
disable |= (1ULL << NVDEV_ENGINE_BSP);
|
||||
disable |= (1ULL << NVDEV_ENGINE_MSVLD);
|
||||
if (!(r00154c & 0x00000040))
|
||||
disable |= (1ULL << NVDEV_ENGINE_VIC);
|
||||
if (!(r00154c & 0x00000200))
|
||||
|
@ -75,7 +75,7 @@ nvc0_devinit_disable(struct nouveau_devinit *devinit)
|
||||
}
|
||||
|
||||
if (r022500 & 0x00000004)
|
||||
disable |= (1ULL << NVDEV_ENGINE_BSP);
|
||||
disable |= (1ULL << NVDEV_ENGINE_MSVLD);
|
||||
if (r022500 & 0x00000008)
|
||||
disable |= (1ULL << NVDEV_ENGINE_VENC);
|
||||
if (r022500 & 0x00000100)
|
||||
|
@ -189,6 +189,9 @@ nv50_fb_intr(struct nouveau_subdev *subdev)
|
||||
const struct nouveau_enum *orig_en = en;
|
||||
while (en->name && en->value == st0 && en->data2) {
|
||||
engine = nouveau_engine(subdev, en->data2);
|
||||
/*XXX: clean this up */
|
||||
if (!engine && en->data2 == NVDEV_ENGINE_BSP)
|
||||
engine = nouveau_engine(subdev, NVDEV_ENGINE_MSVLD);
|
||||
if (engine) {
|
||||
engctx = nouveau_engctx_get(engine, chan);
|
||||
if (engctx)
|
||||
|
@ -31,7 +31,7 @@ nv98_mc_intr[] = {
|
||||
{ 0x00000100, NVDEV_ENGINE_FIFO },
|
||||
{ 0x00001000, NVDEV_ENGINE_GR },
|
||||
{ 0x00004000, NVDEV_ENGINE_CRYPT }, /* NV84:NVA3 */
|
||||
{ 0x00008000, NVDEV_ENGINE_BSP },
|
||||
{ 0x00008000, NVDEV_ENGINE_MSVLD },
|
||||
{ 0x00020000, NVDEV_ENGINE_VP },
|
||||
{ 0x00040000, NVDEV_SUBDEV_PMU }, /* NVA3:NVC0 */
|
||||
{ 0x00080000, NVDEV_SUBDEV_THERM }, /* NVA3:NVC0 */
|
||||
|
@ -34,7 +34,7 @@ nvc0_mc_intr[] = {
|
||||
{ 0x00000100, NVDEV_ENGINE_FIFO },
|
||||
{ 0x00001000, NVDEV_ENGINE_GR },
|
||||
{ 0x00002000, NVDEV_SUBDEV_FB },
|
||||
{ 0x00008000, NVDEV_ENGINE_BSP },
|
||||
{ 0x00008000, NVDEV_ENGINE_MSVLD },
|
||||
{ 0x00040000, NVDEV_SUBDEV_THERM },
|
||||
{ 0x00020000, NVDEV_ENGINE_VP },
|
||||
{ 0x00100000, NVDEV_SUBDEV_TIMER },
|
||||
|
@ -176,7 +176,8 @@ nv50_vm_flush(struct nouveau_vm *vm)
|
||||
case NVDEV_SUBDEV_BAR : vme = 0x06; break;
|
||||
case NVDEV_ENGINE_PPP :
|
||||
case NVDEV_ENGINE_MPEG : vme = 0x08; break;
|
||||
case NVDEV_ENGINE_BSP : vme = 0x09; break;
|
||||
case NVDEV_ENGINE_BSP :
|
||||
case NVDEV_ENGINE_MSVLD: vme = 0x09; break;
|
||||
case NVDEV_ENGINE_CRYPT: vme = 0x0a; break;
|
||||
case NVDEV_ENGINE_COPY0: vme = 0x0d; break;
|
||||
default:
|
||||
|
Loading…
Reference in New Issue
Block a user