mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 12:56:45 +07:00
drm/nouveau: remove ability to use external firmware
This was always really a developer option, and if it's really necessary we can hack this in ourselves. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
631872155f
commit
ec91db269e
@ -9,7 +9,7 @@ nouveau-y := nouveau_drv.o nouveau_state.o nouveau_channel.o nouveau_mem.o \
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nouveau_bo.o nouveau_fence.o nouveau_gem.o nouveau_ttm.o \
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nouveau_hw.o nouveau_calc.o nouveau_bios.o nouveau_i2c.o \
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nouveau_display.o nouveau_connector.o nouveau_fbcon.o \
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nouveau_dp.o nouveau_grctx.o \
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nouveau_dp.o \
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nv04_timer.o \
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nv04_mc.o nv40_mc.o nv50_mc.o \
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nv04_fb.o nv10_fb.o nv40_fb.o nv50_fb.o \
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@ -35,10 +35,6 @@
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#include "drm_pciids.h"
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MODULE_PARM_DESC(ctxfw, "Use external firmware blob for grctx init (NV40)");
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int nouveau_ctxfw = 0;
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module_param_named(ctxfw, nouveau_ctxfw, int, 0400);
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MODULE_PARM_DESC(noagp, "Disable AGP");
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int nouveau_noagp;
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module_param_named(noagp, nouveau_noagp, int, 0400);
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@ -330,8 +330,6 @@ struct nouveau_pgraph_object_class {
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struct nouveau_pgraph_engine {
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struct nouveau_pgraph_object_class *grclass;
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bool accel_blocked;
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void *ctxprog;
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void *ctxvals;
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int grctx_size;
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int (*init)(struct drm_device *);
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@ -665,7 +663,6 @@ extern int nouveau_tv_disable;
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extern char *nouveau_tv_norm;
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extern int nouveau_reg_debug;
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extern char *nouveau_vbios;
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extern int nouveau_ctxfw;
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extern int nouveau_ignorelid;
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extern int nouveau_nofbaccel;
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extern int nouveau_noaccel;
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@ -1010,12 +1007,6 @@ extern int nv50_graph_unload_context(struct drm_device *);
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extern void nv50_graph_context_switch(struct drm_device *);
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extern int nv50_grctx_init(struct nouveau_grctx *);
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/* nouveau_grctx.c */
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extern int nouveau_grctx_prog_load(struct drm_device *);
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extern void nouveau_grctx_vals_load(struct drm_device *,
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struct nouveau_gpuobj *);
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extern void nouveau_grctx_fini(struct drm_device *);
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/* nv04_instmem.c */
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extern int nv04_instmem_init(struct drm_device *);
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extern void nv04_instmem_takedown(struct drm_device *);
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@ -1,160 +0,0 @@
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/*
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* Copyright 2009 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include <linux/firmware.h>
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#include <linux/slab.h>
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#include "drmP.h"
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#include "nouveau_drv.h"
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struct nouveau_ctxprog {
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uint32_t signature;
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uint8_t version;
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uint16_t length;
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uint32_t data[];
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} __attribute__ ((packed));
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struct nouveau_ctxvals {
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uint32_t signature;
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uint8_t version;
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uint32_t length;
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struct {
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uint32_t offset;
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uint32_t value;
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} data[];
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} __attribute__ ((packed));
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int
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nouveau_grctx_prog_load(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
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const int chipset = dev_priv->chipset;
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const struct firmware *fw;
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const struct nouveau_ctxprog *cp;
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const struct nouveau_ctxvals *cv;
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char name[32];
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int ret, i;
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if (pgraph->accel_blocked)
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return -ENODEV;
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if (!pgraph->ctxprog) {
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sprintf(name, "nouveau/nv%02x.ctxprog", chipset);
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ret = request_firmware(&fw, name, &dev->pdev->dev);
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if (ret) {
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NV_ERROR(dev, "No ctxprog for NV%02x\n", chipset);
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return ret;
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}
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pgraph->ctxprog = kmemdup(fw->data, fw->size, GFP_KERNEL);
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if (!pgraph->ctxprog) {
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NV_ERROR(dev, "OOM copying ctxprog\n");
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release_firmware(fw);
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return -ENOMEM;
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}
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cp = pgraph->ctxprog;
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if (le32_to_cpu(cp->signature) != 0x5043564e ||
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cp->version != 0 ||
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le16_to_cpu(cp->length) != ((fw->size - 7) / 4)) {
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NV_ERROR(dev, "ctxprog invalid\n");
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release_firmware(fw);
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nouveau_grctx_fini(dev);
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return -EINVAL;
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}
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release_firmware(fw);
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}
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if (!pgraph->ctxvals) {
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sprintf(name, "nouveau/nv%02x.ctxvals", chipset);
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ret = request_firmware(&fw, name, &dev->pdev->dev);
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if (ret) {
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NV_ERROR(dev, "No ctxvals for NV%02x\n", chipset);
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nouveau_grctx_fini(dev);
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return ret;
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}
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pgraph->ctxvals = kmemdup(fw->data, fw->size, GFP_KERNEL);
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if (!pgraph->ctxvals) {
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NV_ERROR(dev, "OOM copying ctxvals\n");
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release_firmware(fw);
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nouveau_grctx_fini(dev);
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return -ENOMEM;
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}
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cv = (void *)pgraph->ctxvals;
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if (le32_to_cpu(cv->signature) != 0x5643564e ||
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cv->version != 0 ||
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le32_to_cpu(cv->length) != ((fw->size - 9) / 8)) {
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NV_ERROR(dev, "ctxvals invalid\n");
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release_firmware(fw);
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nouveau_grctx_fini(dev);
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return -EINVAL;
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}
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release_firmware(fw);
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}
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cp = pgraph->ctxprog;
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
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for (i = 0; i < le16_to_cpu(cp->length); i++)
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA,
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le32_to_cpu(cp->data[i]));
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return 0;
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}
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void
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nouveau_grctx_fini(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
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if (pgraph->ctxprog) {
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kfree(pgraph->ctxprog);
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pgraph->ctxprog = NULL;
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}
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if (pgraph->ctxvals) {
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kfree(pgraph->ctxprog);
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pgraph->ctxvals = NULL;
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}
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}
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void
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nouveau_grctx_vals_load(struct drm_device *dev, struct nouveau_gpuobj *ctx)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
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struct nouveau_ctxvals *cv = pgraph->ctxvals;
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int i;
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if (!cv)
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return;
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for (i = 0; i < le32_to_cpu(cv->length); i++)
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nv_wo32(dev, ctx, le32_to_cpu(cv->data[i].offset),
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le32_to_cpu(cv->data[i].value));
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}
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@ -58,6 +58,7 @@ nv40_graph_create_context(struct nouveau_channel *chan)
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
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struct nouveau_grctx ctx = {};
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int ret;
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ret = nouveau_gpuobj_new_ref(dev, chan, NULL, 0, pgraph->grctx_size,
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@ -67,16 +68,11 @@ nv40_graph_create_context(struct nouveau_channel *chan)
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return ret;
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/* Initialise default context values */
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if (!pgraph->ctxprog) {
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struct nouveau_grctx ctx = {};
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ctx.dev = chan->dev;
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ctx.mode = NOUVEAU_GRCTX_VALS;
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ctx.data = chan->ramin_grctx->gpuobj;
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nv40_grctx_init(&ctx);
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ctx.dev = chan->dev;
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ctx.mode = NOUVEAU_GRCTX_VALS;
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ctx.data = chan->ramin_grctx->gpuobj;
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nv40_grctx_init(&ctx);
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} else {
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nouveau_grctx_vals_load(dev, chan->ramin_grctx->gpuobj);
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}
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nv_wo32(dev, chan->ramin_grctx->gpuobj, 0,
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chan->ramin_grctx->gpuobj->im_pramin->start);
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return 0;
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@ -236,7 +232,8 @@ nv40_graph_init(struct drm_device *dev)
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struct drm_nouveau_private *dev_priv =
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(struct drm_nouveau_private *)dev->dev_private;
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struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
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uint32_t vramsz;
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struct nouveau_grctx ctx = {};
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uint32_t vramsz, *cp;
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int i, j;
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nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
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@ -244,32 +241,22 @@ nv40_graph_init(struct drm_device *dev)
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nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
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NV_PMC_ENABLE_PGRAPH);
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if (nouveau_ctxfw) {
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nouveau_grctx_prog_load(dev);
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dev_priv->engine.graph.grctx_size = 175 * 1024;
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}
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cp = kmalloc(sizeof(*cp) * 256, GFP_KERNEL);
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if (!cp)
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return -ENOMEM;
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if (!dev_priv->engine.graph.ctxprog) {
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struct nouveau_grctx ctx = {};
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uint32_t *cp;
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ctx.dev = dev;
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ctx.mode = NOUVEAU_GRCTX_PROG;
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ctx.data = cp;
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ctx.ctxprog_max = 256;
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nv40_grctx_init(&ctx);
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dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
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cp = kmalloc(sizeof(*cp) * 256, GFP_KERNEL);
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if (!cp)
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return -ENOMEM;
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
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for (i = 0; i < ctx.ctxprog_len; i++)
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
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ctx.dev = dev;
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ctx.mode = NOUVEAU_GRCTX_PROG;
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ctx.data = cp;
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ctx.ctxprog_max = 256;
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nv40_grctx_init(&ctx);
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dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
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for (i = 0; i < ctx.ctxprog_len; i++)
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
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kfree(cp);
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}
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kfree(cp);
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/* No context present currently */
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
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@ -405,7 +392,6 @@ nv40_graph_init(struct drm_device *dev)
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void nv40_graph_takedown(struct drm_device *dev)
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{
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nouveau_grctx_fini(dev);
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}
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struct nouveau_pgraph_object_class nv40_graph_grclass[] = {
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@ -103,37 +103,33 @@ static int
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nv50_graph_init_ctxctl(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_grctx ctx = {};
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uint32_t *cp;
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int i;
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NV_DEBUG(dev, "\n");
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if (nouveau_ctxfw) {
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nouveau_grctx_prog_load(dev);
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dev_priv->engine.graph.grctx_size = 0x70000;
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cp = kmalloc(512 * 4, GFP_KERNEL);
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if (!cp) {
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NV_ERROR(dev, "failed to allocate ctxprog\n");
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dev_priv->engine.graph.accel_blocked = true;
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return 0;
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}
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if (!dev_priv->engine.graph.ctxprog) {
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struct nouveau_grctx ctx = {};
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uint32_t *cp = kmalloc(512 * 4, GFP_KERNEL);
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int i;
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if (!cp) {
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NV_ERROR(dev, "Couldn't alloc ctxprog! Disabling acceleration.\n");
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dev_priv->engine.graph.accel_blocked = true;
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return 0;
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}
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ctx.dev = dev;
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ctx.mode = NOUVEAU_GRCTX_PROG;
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ctx.data = cp;
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ctx.ctxprog_max = 512;
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if (!nv50_grctx_init(&ctx)) {
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dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
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for (i = 0; i < ctx.ctxprog_len; i++)
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
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} else {
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dev_priv->engine.graph.accel_blocked = true;
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}
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kfree(cp);
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ctx.dev = dev;
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ctx.mode = NOUVEAU_GRCTX_PROG;
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ctx.data = cp;
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ctx.ctxprog_max = 512;
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if (!nv50_grctx_init(&ctx)) {
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dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
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for (i = 0; i < ctx.ctxprog_len; i++)
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
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} else {
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dev_priv->engine.graph.accel_blocked = true;
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}
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kfree(cp);
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nv_wr32(dev, 0x400320, 4);
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0);
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@ -164,7 +160,6 @@ void
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nv50_graph_takedown(struct drm_device *dev)
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{
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NV_DEBUG(dev, "\n");
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nouveau_grctx_fini(dev);
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}
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void
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@ -214,6 +209,7 @@ nv50_graph_create_context(struct nouveau_channel *chan)
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struct nouveau_gpuobj *ramin = chan->ramin->gpuobj;
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struct nouveau_gpuobj *obj;
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struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
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struct nouveau_grctx ctx = {};
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int hdr, ret;
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NV_DEBUG(dev, "ch%d\n", chan->id);
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@ -234,15 +230,11 @@ nv50_graph_create_context(struct nouveau_channel *chan)
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nv_wo32(dev, ramin, (hdr + 0x10)/4, 0);
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nv_wo32(dev, ramin, (hdr + 0x14)/4, 0x00010000);
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if (!pgraph->ctxprog) {
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struct nouveau_grctx ctx = {};
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ctx.dev = chan->dev;
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ctx.mode = NOUVEAU_GRCTX_VALS;
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ctx.data = obj;
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nv50_grctx_init(&ctx);
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} else {
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nouveau_grctx_vals_load(dev, obj);
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}
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ctx.dev = chan->dev;
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ctx.mode = NOUVEAU_GRCTX_VALS;
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ctx.data = obj;
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nv50_grctx_init(&ctx);
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nv_wo32(dev, obj, 0x00000/4, chan->ramin->instance >> 12);
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dev_priv->engine.instmem.flush(dev);
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