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irqchip mvebu fixes for v3.14
- orion: - fixes for clearing bridge cause register, and clearing stale interrupts -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAABAgAGBQJTB8pSAAoJEP45WPkGe8ZnDsMP/0SuXXVsAV9tQJL5Nwtx0WwJ bLxYaT09y4//fcsJ7RnZygixxqdTGh721yO8Al7PGf1u5XeOkZWhvIjUatB1D8kP 7awHqzqM1g+rPVNzM/0sS8KNPz8FahAAvCP6Oynm6YPFE7uxpOPzqwij4r7u/dYE OBpZwjRJKomdiI5ixwuuR7uGrLWhPZBtqlptvUyWdElPgaLztStmhOqs0l2AVOqI UzuZMwJE/DP5MJ3yCThH0b7+1s3H8OZvkSRAgIHXeU0TNXhsomyh6oOmXsn23LXX jkoHfh+FO+XBZZsIEFR2cgJBoIp/NdvcqT9/UiaIdBagKfCtpPCTUqybS/F9qgVt 2mwUtBXFTzkrAoSUHRLcvlrbhMwmIodHu3TUcHbXyPtTBG7YqoXsCWdr/pTUxmep sexZ6kNNdAh1tMfsvnvXdhPZKanuPk9K2vXrasu0oAbUl2Ce0XEhjYDAJ4EhSmox 9r6LVp9DZytacDaNWzD4NV2hOHixzSSpMk5dg85wGx7c+Ump85ZDxDCHC4w2nLyJ 2ZH+2vH/5gifTHTHYrkOB0gf9+NVzfs8WXJuMufKg5B3QSudQXkKE+B0I7yhxXdG LKSkK2LFMGXfiPGqeW2gWBHfSlodICXY46jHgUeXPEsx6ue3i/xPIWEa4twOrOo5 uBZc3pDwB7nbQCCgeg8M =r7Cd -----END PGP SIGNATURE----- Merge tag 'irqchip-mvebu-fixes-3.14' of git://git.infradead.org/linux-mvebu into irq/urgent irqchip mvebu fixes for v3.14 - orion: - fixes for clearing bridge cause register, and clearing stale interrupts Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
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commit
ec79b577f0
@ -111,7 +111,8 @@ IRQCHIP_DECLARE(orion_intc, "marvell,orion-intc", orion_irq_init);
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static void orion_bridge_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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struct irq_domain *d = irq_get_handler_data(irq);
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struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, irq);
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struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, 0);
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u32 stat = readl_relaxed(gc->reg_base + ORION_BRIDGE_IRQ_CAUSE) &
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gc->mask_cache;
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@ -123,6 +124,19 @@ static void orion_bridge_irq_handler(unsigned int irq, struct irq_desc *desc)
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}
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}
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/*
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* Bridge IRQ_CAUSE is asserted regardless of IRQ_MASK register.
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* To avoid interrupt events on stale irqs, we clear them before unmask.
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*/
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static unsigned int orion_bridge_irq_startup(struct irq_data *d)
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{
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struct irq_chip_type *ct = irq_data_get_chip_type(d);
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ct->chip.irq_ack(d);
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ct->chip.irq_unmask(d);
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return 0;
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}
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static int __init orion_bridge_irq_init(struct device_node *np,
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struct device_node *parent)
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{
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@ -143,7 +157,7 @@ static int __init orion_bridge_irq_init(struct device_node *np,
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}
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ret = irq_alloc_domain_generic_chips(domain, nrirqs, 1, np->name,
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handle_level_irq, clr, 0, IRQ_GC_INIT_MASK_CACHE);
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handle_edge_irq, clr, 0, IRQ_GC_INIT_MASK_CACHE);
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if (ret) {
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pr_err("%s: unable to alloc irq domain gc\n", np->name);
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return ret;
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@ -176,12 +190,14 @@ static int __init orion_bridge_irq_init(struct device_node *np,
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gc->chip_types[0].regs.ack = ORION_BRIDGE_IRQ_CAUSE;
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gc->chip_types[0].regs.mask = ORION_BRIDGE_IRQ_MASK;
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gc->chip_types[0].chip.irq_startup = orion_bridge_irq_startup;
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gc->chip_types[0].chip.irq_ack = irq_gc_ack_clr_bit;
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gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
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gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
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/* mask all interrupts */
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/* mask and clear all interrupts */
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writel(0, gc->reg_base + ORION_BRIDGE_IRQ_MASK);
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writel(0, gc->reg_base + ORION_BRIDGE_IRQ_CAUSE);
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irq_set_handler_data(irq, domain);
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irq_set_chained_handler(irq, orion_bridge_irq_handler);
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