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drm/i915: Remove superfluous posting reads after clear GGTT
The barrier here is not required - we apply the barrier before the range is ever reused by the GPU instead. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170215084357.19977-16-chris@chris-wilson.co.uk
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@ -2184,7 +2184,6 @@ static void gen8_ggtt_clear_range(struct i915_address_space *vm,
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for (i = 0; i < num_entries; i++)
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gen8_set_pte(>t_base[i], scratch_pte);
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readl(gtt_base);
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}
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static void gen6_ggtt_clear_range(struct i915_address_space *vm,
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@ -2209,7 +2208,6 @@ static void gen6_ggtt_clear_range(struct i915_address_space *vm,
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for (i = 0; i < num_entries; i++)
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iowrite32(scratch_pte, >t_base[i]);
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readl(gtt_base);
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}
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static void i915_ggtt_insert_page(struct i915_address_space *vm,
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@ -2233,7 +2231,6 @@ static void i915_ggtt_insert_entries(struct i915_address_space *vm,
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AGP_USER_MEMORY : AGP_USER_CACHED_MEMORY;
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intel_gtt_insert_sg_entries(pages, start >> PAGE_SHIFT, flags);
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}
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static void i915_ggtt_clear_range(struct i915_address_space *vm,
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