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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ARM: dts: r8a7742: Initial SoC device tree
The initial R8A7742 SoC device tree including CPU[0-8], PMU, PFC, CPG, RST, SYSC, ICRAM[0-2], SCIFA2, MMC1, DMAC[0-1], GIC, PRR, timer and the required clock descriptions. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1588542414-14826-7-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar
Geert Uytterhoeven
parent
ca0762ee44
commit
eb4cdda7a3
389
arch/arm/boot/dts/r8a7742.dtsi
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389
arch/arm/boot/dts/r8a7742.dtsi
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@ -0,0 +1,389 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for the r8a7742 SoC
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*
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* Copyright (C) 2020 Renesas Electronics Corp.
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*/
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#include <dt-bindings/clock/r8a7742-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/power/r8a7742-sysc.h>
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/ {
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compatible = "renesas,r8a7742";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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clock-frequency = <1400000000>;
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clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
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power-domains = <&sysc R8A7742_PD_CA15_CPU0>;
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next-level-cache = <&L2_CA15>;
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capacity-dmips-mhz = <1024>;
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voltage-tolerance = <1>; /* 1% */
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clock-latency = <300000>; /* 300 us */
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/* kHz - uV - OPPs unknown yet */
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operating-points = <1400000 1000000>,
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<1225000 1000000>,
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<1050000 1000000>,
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< 875000 1000000>,
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< 700000 1000000>,
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< 350000 1000000>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <1>;
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clock-frequency = <1400000000>;
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clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
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power-domains = <&sysc R8A7742_PD_CA15_CPU1>;
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next-level-cache = <&L2_CA15>;
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capacity-dmips-mhz = <1024>;
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voltage-tolerance = <1>; /* 1% */
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clock-latency = <300000>; /* 300 us */
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/* kHz - uV - OPPs unknown yet */
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operating-points = <1400000 1000000>,
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<1225000 1000000>,
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<1050000 1000000>,
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< 875000 1000000>,
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< 700000 1000000>,
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< 350000 1000000>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <2>;
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clock-frequency = <1400000000>;
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clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
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power-domains = <&sysc R8A7742_PD_CA15_CPU2>;
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next-level-cache = <&L2_CA15>;
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capacity-dmips-mhz = <1024>;
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voltage-tolerance = <1>; /* 1% */
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clock-latency = <300000>; /* 300 us */
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/* kHz - uV - OPPs unknown yet */
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operating-points = <1400000 1000000>,
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<1225000 1000000>,
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<1050000 1000000>,
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< 875000 1000000>,
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< 700000 1000000>,
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< 350000 1000000>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <3>;
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clock-frequency = <1400000000>;
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clocks = <&cpg CPG_CORE R8A7742_CLK_Z>;
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power-domains = <&sysc R8A7742_PD_CA15_CPU3>;
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next-level-cache = <&L2_CA15>;
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capacity-dmips-mhz = <1024>;
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voltage-tolerance = <1>; /* 1% */
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clock-latency = <300000>; /* 300 us */
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/* kHz - uV - OPPs unknown yet */
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operating-points = <1400000 1000000>,
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<1225000 1000000>,
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<1050000 1000000>,
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< 875000 1000000>,
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< 700000 1000000>,
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< 350000 1000000>;
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};
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cpu4: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x100>;
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clock-frequency = <780000000>;
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clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
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power-domains = <&sysc R8A7742_PD_CA7_CPU0>;
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next-level-cache = <&L2_CA7>;
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};
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cpu5: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x101>;
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clock-frequency = <780000000>;
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clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
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power-domains = <&sysc R8A7742_PD_CA7_CPU1>;
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next-level-cache = <&L2_CA7>;
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};
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cpu6: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x102>;
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clock-frequency = <780000000>;
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clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
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power-domains = <&sysc R8A7742_PD_CA7_CPU2>;
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next-level-cache = <&L2_CA7>;
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};
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cpu7: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x103>;
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clock-frequency = <780000000>;
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clocks = <&cpg CPG_CORE R8A7742_CLK_Z2>;
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power-domains = <&sysc R8A7742_PD_CA7_CPU3>;
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next-level-cache = <&L2_CA7>;
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};
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L2_CA15: cache-controller-0 {
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compatible = "cache";
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power-domains = <&sysc R8A7742_PD_CA15_SCU>;
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cache-unified;
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cache-level = <2>;
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};
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L2_CA7: cache-controller-1 {
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compatible = "cache";
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power-domains = <&sysc R8A7742_PD_CA7_SCU>;
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cache-unified;
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cache-level = <2>;
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};
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};
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/* External root clock */
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extal_clk: extal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board. */
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clock-frequency = <0>;
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};
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pmu-0 {
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compatible = "arm,cortex-a15-pmu";
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interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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pmu-1 {
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compatible = "arm,cortex-a7-pmu";
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interrupts-extended = <&gic GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
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};
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/* External SCIF clock */
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scif_clk: scif {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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/* This value must be overridden by the board. */
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clock-frequency = <0>;
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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pfc: pin-controller@e6060000 {
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compatible = "renesas,pfc-r8a7742";
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reg = <0 0xe6060000 0 0x250>;
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};
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a7742-cpg-mssr";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>, <&usb_extal_clk>;
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clock-names = "extal", "usb_extal";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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};
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rst: reset-controller@e6160000 {
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compatible = "renesas,r8a7742-rst";
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reg = <0 0xe6160000 0 0x0100>;
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a7742-sysc";
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reg = <0 0xe6180000 0 0x0200>;
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#power-domain-cells = <1>;
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};
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icram0: sram@e63a0000 {
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compatible = "mmio-sram";
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reg = <0 0xe63a0000 0 0x12000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0xe63a0000 0x12000>;
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};
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icram1: sram@e63c0000 {
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compatible = "mmio-sram";
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reg = <0 0xe63c0000 0 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0xe63c0000 0x1000>;
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smp-sram@0 {
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compatible = "renesas,smp-sram";
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reg = <0 0x100>;
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};
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};
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icram2: sram@e6300000 {
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compatible = "mmio-sram";
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reg = <0 0xe6300000 0 0x40000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0xe6300000 0x40000>;
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};
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dmac0: dma-controller@e6700000 {
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compatible = "renesas,dmac-r8a7742",
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"renesas,rcar-dmac";
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reg = <0 0xe6700000 0 0x20000>;
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interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14";
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clocks = <&cpg CPG_MOD 219>;
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clock-names = "fck";
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power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
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resets = <&cpg 219>;
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#dma-cells = <1>;
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dma-channels = <15>;
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};
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dmac1: dma-controller@e6720000 {
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compatible = "renesas,dmac-r8a7742",
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"renesas,rcar-dmac";
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reg = <0 0xe6720000 0 0x20000>;
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interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error",
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"ch0", "ch1", "ch2", "ch3",
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"ch4", "ch5", "ch6", "ch7",
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"ch8", "ch9", "ch10", "ch11",
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"ch12", "ch13", "ch14";
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clocks = <&cpg CPG_MOD 218>;
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clock-names = "fck";
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power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
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resets = <&cpg 218>;
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#dma-cells = <1>;
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dma-channels = <15>;
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};
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scifa2: serial@e6c60000 {
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compatible = "renesas,scifa-r8a7742",
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"renesas,rcar-gen2-scifa", "renesas,scifa";
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reg = <0 0xe6c60000 0 0x40>;
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interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 202>;
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clock-names = "fck";
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dmas = <&dmac0 0x27>, <&dmac0 0x28>,
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<&dmac1 0x27>, <&dmac1 0x28>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
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resets = <&cpg 202>;
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status = "disabled";
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};
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mmcif1: mmc@ee220000 {
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compatible = "renesas,mmcif-r8a7742",
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"renesas,sh-mmcif";
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reg = <0 0xee220000 0 0x80>;
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interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 305>;
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dmas = <&dmac0 0xe1>, <&dmac0 0xe2>,
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<&dmac1 0xe1>, <&dmac1 0xe2>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
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resets = <&cpg 305>;
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reg-io-width = <4>;
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status = "disabled";
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max-frequency = <97500000>;
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};
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gic: interrupt-controller@f1001000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
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<0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&cpg CPG_MOD 408>;
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clock-names = "clk";
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power-domains = <&sysc R8A7742_PD_ALWAYS_ON>;
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resets = <&cpg 408>;
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};
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prr: chipid@ff000044 {
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compatible = "renesas,prr";
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reg = <0 0xff000044 0 4>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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};
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/* External USB clock - can be overridden by the board */
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usb_extal_clk: usb_extal {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <48000000>;
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};
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};
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