mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-04 08:06:43 +07:00
drm/i915: split PLL update code out of i9xx_crtc_mode_set
Makes it more readable and maintainable. ValleyView will add its own PLL update function in a later patch. v2: split LVDS bits out of this patch (Daniel) v3: fix dropped DP dithering hunk (Daniel) Acked-by: Ben Widawsky <ben@bwidawsk.net> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> danvet: - fixup spurious whitespace change - reorder patches to fix bisect breakage Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter
parent
93e537a10f
commit
eb1cbe4848
@ -5190,6 +5190,177 @@ static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
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I915_WRITE(LVDS, temp);
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}
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static void i9xx_update_pll(struct drm_crtc *crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode,
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intel_clock_t *clock, intel_clock_t *reduced_clock,
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int num_connectors)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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u32 dpll;
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bool is_sdvo;
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is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
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intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
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dpll = DPLL_VGA_MODE_DIS;
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
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dpll |= DPLLB_MODE_LVDS;
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else
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dpll |= DPLLB_MODE_DAC_SERIAL;
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if (is_sdvo) {
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int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
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if (pixel_multiplier > 1) {
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if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
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dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
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}
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dpll |= DPLL_DVO_HIGH_SPEED;
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}
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
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dpll |= DPLL_DVO_HIGH_SPEED;
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/* compute bitmask from p1 value */
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if (IS_PINEVIEW(dev))
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dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
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else {
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dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
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if (IS_G4X(dev) && reduced_clock)
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dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
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}
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switch (clock->p2) {
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case 5:
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dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
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break;
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case 7:
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dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
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break;
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case 10:
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dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
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break;
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case 14:
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dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
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break;
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}
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if (INTEL_INFO(dev)->gen >= 4)
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dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
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if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
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dpll |= PLL_REF_INPUT_TVCLKINBC;
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else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
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/* XXX: just matching BIOS for now */
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/* dpll |= PLL_REF_INPUT_TVCLKINBC; */
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dpll |= 3;
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else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
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intel_panel_use_ssc(dev_priv) && num_connectors < 2)
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dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
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else
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dpll |= PLL_REF_INPUT_DREFCLK;
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dpll |= DPLL_VCO_ENABLE;
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I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
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POSTING_READ(DPLL(pipe));
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udelay(150);
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/* The LVDS pin pair needs to be on before the DPLLs are enabled.
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* This is an exception to the general rule that mode_set doesn't turn
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* things on.
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*/
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
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intel_update_lvds(crtc, clock, adjusted_mode);
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
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intel_dp_set_m_n(crtc, mode, adjusted_mode);
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I915_WRITE(DPLL(pipe), dpll);
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/* Wait for the clocks to stabilize. */
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POSTING_READ(DPLL(pipe));
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udelay(150);
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if (INTEL_INFO(dev)->gen >= 4) {
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u32 temp = 0;
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if (is_sdvo) {
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temp = intel_mode_get_pixel_multiplier(adjusted_mode);
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if (temp > 1)
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temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
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else
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temp = 0;
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}
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I915_WRITE(DPLL_MD(pipe), temp);
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} else {
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/* The pixel multiplier can only be updated once the
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* DPLL is enabled and the clocks are stable.
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*
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* So write it again.
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*/
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I915_WRITE(DPLL(pipe), dpll);
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}
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}
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static void i8xx_update_pll(struct drm_crtc *crtc,
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struct drm_display_mode *adjusted_mode,
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intel_clock_t *clock,
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int num_connectors)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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u32 dpll;
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dpll = DPLL_VGA_MODE_DIS;
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
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} else {
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if (clock->p1 == 2)
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dpll |= PLL_P1_DIVIDE_BY_TWO;
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else
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dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
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if (clock->p2 == 4)
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dpll |= PLL_P2_DIVIDE_BY_4;
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}
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
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/* XXX: just matching BIOS for now */
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/* dpll |= PLL_REF_INPUT_TVCLKINBC; */
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dpll |= 3;
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else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
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intel_panel_use_ssc(dev_priv) && num_connectors < 2)
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dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
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else
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dpll |= PLL_REF_INPUT_DREFCLK;
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dpll |= DPLL_VCO_ENABLE;
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I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
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POSTING_READ(DPLL(pipe));
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udelay(150);
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I915_WRITE(DPLL(pipe), dpll);
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/* Wait for the clocks to stabilize. */
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POSTING_READ(DPLL(pipe));
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udelay(150);
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/* The LVDS pin pair needs to be on before the DPLLs are enabled.
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* This is an exception to the general rule that mode_set doesn't turn
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* things on.
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*/
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
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intel_update_lvds(crtc, clock, adjusted_mode);
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/* The pixel multiplier can only be updated once the
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* DPLL is enabled and the clocks are stable.
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*
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* So write it again.
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*/
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I915_WRITE(DPLL(pipe), dpll);
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}
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static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode,
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@ -5203,14 +5374,13 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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int plane = intel_crtc->plane;
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int refclk, num_connectors = 0;
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intel_clock_t clock, reduced_clock;
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u32 dpll, dspcntr, pipeconf, vsyncshift;
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bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
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bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
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u32 dspcntr, pipeconf, vsyncshift;
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bool ok, has_reduced_clock = false, is_sdvo = false;
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bool is_lvds = false, is_tv = false, is_dp = false;
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struct drm_mode_config *mode_config = &dev->mode_config;
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struct intel_encoder *encoder;
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const intel_limit_t *limit;
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int ret;
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u32 temp;
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list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
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if (encoder->base.crtc != crtc)
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@ -5226,15 +5396,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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if (encoder->needs_tv_clock)
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is_tv = true;
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break;
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case INTEL_OUTPUT_DVO:
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is_dvo = true;
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break;
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case INTEL_OUTPUT_TVOUT:
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is_tv = true;
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break;
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case INTEL_OUTPUT_ANALOG:
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is_crt = true;
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break;
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case INTEL_OUTPUT_DISPLAYPORT:
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is_dp = true;
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break;
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@ -5281,71 +5445,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
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&reduced_clock : NULL);
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dpll = DPLL_VGA_MODE_DIS;
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if (!IS_GEN2(dev)) {
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if (is_lvds)
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dpll |= DPLLB_MODE_LVDS;
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else
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dpll |= DPLLB_MODE_DAC_SERIAL;
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if (is_sdvo) {
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int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
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if (pixel_multiplier > 1) {
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if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
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dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
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}
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dpll |= DPLL_DVO_HIGH_SPEED;
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}
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if (is_dp)
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dpll |= DPLL_DVO_HIGH_SPEED;
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/* compute bitmask from p1 value */
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if (IS_PINEVIEW(dev))
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dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
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else {
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dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
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if (IS_G4X(dev) && has_reduced_clock)
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dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
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}
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switch (clock.p2) {
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case 5:
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dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
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break;
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case 7:
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dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
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break;
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case 10:
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dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
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break;
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case 14:
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dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
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break;
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}
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if (INTEL_INFO(dev)->gen >= 4)
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dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
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} else {
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if (is_lvds) {
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dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
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} else {
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if (clock.p1 == 2)
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dpll |= PLL_P1_DIVIDE_BY_TWO;
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else
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dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
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if (clock.p2 == 4)
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dpll |= PLL_P2_DIVIDE_BY_4;
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}
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}
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if (is_sdvo && is_tv)
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dpll |= PLL_REF_INPUT_TVCLKINBC;
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else if (is_tv)
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/* XXX: just matching BIOS for now */
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/* dpll |= PLL_REF_INPUT_TVCLKINBC; */
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dpll |= 3;
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else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
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dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
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if (IS_GEN2(dev))
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i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
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else
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dpll |= PLL_REF_INPUT_DREFCLK;
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i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
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has_reduced_clock ? &reduced_clock : NULL,
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num_connectors);
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/* setup pipeconf */
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pipeconf = I915_READ(PIPECONF(pipe));
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@ -5382,52 +5487,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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}
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}
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dpll |= DPLL_VCO_ENABLE;
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DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
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drm_mode_debug_printmodeline(mode);
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I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
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POSTING_READ(DPLL(pipe));
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udelay(150);
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/* The LVDS pin pair needs to be on before the DPLLs are enabled.
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* This is an exception to the general rule that mode_set doesn't turn
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* things on.
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*/
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
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intel_update_lvds(crtc, &clock, adjusted_mode);
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if (is_dp) {
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intel_dp_set_m_n(crtc, mode, adjusted_mode);
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}
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I915_WRITE(DPLL(pipe), dpll);
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/* Wait for the clocks to stabilize. */
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POSTING_READ(DPLL(pipe));
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udelay(150);
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if (INTEL_INFO(dev)->gen >= 4) {
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temp = 0;
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if (is_sdvo) {
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temp = intel_mode_get_pixel_multiplier(adjusted_mode);
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if (temp > 1)
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temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
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else
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temp = 0;
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}
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I915_WRITE(DPLL_MD(pipe), temp);
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} else {
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/* The pixel multiplier can only be updated once the
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* DPLL is enabled and the clocks are stable.
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*
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* So write it again.
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*/
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I915_WRITE(DPLL(pipe), dpll);
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}
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if (HAS_PIPE_CXSR(dev)) {
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if (intel_crtc->lowfreq_avail) {
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DRM_DEBUG_KMS("enabling CxSR downclocking\n");
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