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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 15:15:59 +07:00
iwlwifi: pcie: clarify TX queue need_update handling
Similar to the recent RX queue patch, this changes the need_update handling for the TX queues to be clearer and only done when needed. Signed-off-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
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@ -365,7 +365,7 @@ void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo,
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void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue);
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int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
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struct iwl_device_cmd *dev_cmd, int txq_id);
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void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_txq *txq);
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void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans);
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int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd);
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void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
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struct iwl_rx_cmd_buffer *rxb, int handler_status);
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@ -889,7 +889,6 @@ irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
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struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
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u32 inta = 0;
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u32 handled = 0;
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u32 i;
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lock_map_acquire(&trans->sync_cmd_lockdep_map);
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@ -1042,11 +1041,7 @@ irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
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if (inta & CSR_INT_BIT_WAKEUP) {
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IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
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iwl_pcie_rxq_check_wrptr(trans);
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for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
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spin_lock(&trans_pcie->txq[i].lock);
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iwl_pcie_txq_inc_wr_ptr(trans, &trans_pcie->txq[i]);
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spin_unlock(&trans_pcie->txq[i].lock);
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}
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iwl_pcie_txq_check_wrptrs(trans);
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isr_stats->wakeup++;
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@ -287,14 +287,14 @@ static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
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/*
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* iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
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*/
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void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_txq *txq)
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static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
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struct iwl_txq *txq)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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u32 reg = 0;
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int txq_id = txq->q.id;
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if (!txq->need_update)
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return;
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lockdep_assert_held(&txq->lock);
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/*
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* explicitly wake up the NIC if:
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@ -317,6 +317,7 @@ void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_txq *txq)
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txq_id, reg);
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iwl_set_bit(trans, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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txq->need_update = true;
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return;
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}
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}
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@ -327,8 +328,23 @@ void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans, struct iwl_txq *txq)
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*/
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IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->q.write_ptr);
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iwl_write32(trans, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
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}
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txq->need_update = false;
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void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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int i;
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for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
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struct iwl_txq *txq = &trans_pcie->txq[i];
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spin_lock(&txq->lock);
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if (trans_pcie->txq[i].need_update) {
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iwl_pcie_txq_inc_wr_ptr(trans, txq);
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trans_pcie->txq[i].need_update = false;
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}
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spin_unlock(&txq->lock);
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}
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}
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static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
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@ -1393,8 +1409,6 @@ static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
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kfree(txq->entries[idx].free_buf);
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txq->entries[idx].free_buf = dup_buf;
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txq->need_update = true;
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trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr);
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/* start timer if queue currently empty */
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@ -1664,7 +1678,7 @@ int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
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dma_addr_t tb0_phys, tb1_phys, scratch_phys;
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void *tb1_addr;
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u16 len, tb1_len, tb2_len;
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bool wait_write_ptr = false;
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bool wait_write_ptr;
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__le16 fc = hdr->frame_control;
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u8 hdr_len = ieee80211_hdrlen(fc);
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u16 wifi_seq;
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@ -1765,12 +1779,7 @@ int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
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trace_iwlwifi_dev_tx_data(trans->dev, skb,
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skb->data + hdr_len, tb2_len);
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if (!ieee80211_has_morefrags(fc)) {
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txq->need_update = true;
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} else {
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wait_write_ptr = true;
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txq->need_update = false;
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}
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wait_write_ptr = ieee80211_has_morefrags(fc);
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/* start timer if queue currently empty */
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if (txq->need_update && q->read_ptr == q->write_ptr &&
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@ -1779,19 +1788,18 @@ int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
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/* Tell device the write index *just past* this latest filled TFD */
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q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
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iwl_pcie_txq_inc_wr_ptr(trans, txq);
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if (!wait_write_ptr)
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iwl_pcie_txq_inc_wr_ptr(trans, txq);
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/*
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* At this point the frame is "transmitted" successfully
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* and we will get a TX status notification eventually.
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*/
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if (iwl_queue_space(q) < q->high_mark) {
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if (wait_write_ptr) {
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txq->need_update = true;
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if (wait_write_ptr)
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iwl_pcie_txq_inc_wr_ptr(trans, txq);
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} else {
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else
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iwl_stop_queue(trans, txq);
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}
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}
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spin_unlock(&txq->lock);
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return 0;
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