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drm/amdgpu: add VCE VM mode support
This adds VCE VM mode support from Stoney onwards. Session tracking is an open issue, yet to be supported. v2: Fixed warnings from checkpatch.pl Signed-off-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -775,6 +775,39 @@ static int vce_v3_0_set_powergating_state(void *handle,
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return vce_v3_0_start(adev);
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}
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static void vce_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
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struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch)
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{
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amdgpu_ring_write(ring, VCE_CMD_IB_VM);
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amdgpu_ring_write(ring, vm_id);
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amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
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amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
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amdgpu_ring_write(ring, ib->length_dw);
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}
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static void vce_v3_0_emit_vm_flush(struct amdgpu_ring *ring,
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unsigned int vm_id, uint64_t pd_addr)
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{
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amdgpu_ring_write(ring, VCE_CMD_UPDATE_PTB);
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amdgpu_ring_write(ring, vm_id);
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amdgpu_ring_write(ring, pd_addr >> 12);
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amdgpu_ring_write(ring, VCE_CMD_FLUSH_TLB);
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amdgpu_ring_write(ring, vm_id);
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amdgpu_ring_write(ring, VCE_CMD_END);
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}
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static void vce_v3_0_emit_pipeline_sync(struct amdgpu_ring *ring)
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{
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uint32_t seq = ring->fence_drv.sync_seq;
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uint64_t addr = ring->fence_drv.gpu_addr;
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amdgpu_ring_write(ring, VCE_CMD_WAIT_GE);
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amdgpu_ring_write(ring, lower_32_bits(addr));
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amdgpu_ring_write(ring, upper_32_bits(addr));
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amdgpu_ring_write(ring, seq);
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}
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const struct amd_ip_funcs vce_v3_0_ip_funcs = {
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.name = "vce_v3_0",
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.early_init = vce_v3_0_early_init,
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@ -795,7 +828,7 @@ const struct amd_ip_funcs vce_v3_0_ip_funcs = {
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.set_powergating_state = vce_v3_0_set_powergating_state,
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};
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static const struct amdgpu_ring_funcs vce_v3_0_ring_funcs = {
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static const struct amdgpu_ring_funcs vce_v3_0_ring_phys_funcs = {
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.get_rptr = vce_v3_0_ring_get_rptr,
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.get_wptr = vce_v3_0_ring_get_wptr,
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.set_wptr = vce_v3_0_ring_set_wptr,
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@ -810,12 +843,36 @@ static const struct amdgpu_ring_funcs vce_v3_0_ring_funcs = {
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.end_use = amdgpu_vce_ring_end_use,
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};
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static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = {
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.get_rptr = vce_v3_0_ring_get_rptr,
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.get_wptr = vce_v3_0_ring_get_wptr,
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.set_wptr = vce_v3_0_ring_set_wptr,
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.parse_cs = NULL,
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.emit_ib = vce_v3_0_ring_emit_ib,
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.emit_vm_flush = vce_v3_0_emit_vm_flush,
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.emit_pipeline_sync = vce_v3_0_emit_pipeline_sync,
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.emit_fence = amdgpu_vce_ring_emit_fence,
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.test_ring = amdgpu_vce_ring_test_ring,
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.test_ib = amdgpu_vce_ring_test_ib,
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.insert_nop = amdgpu_ring_insert_nop,
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.pad_ib = amdgpu_ring_generic_pad_ib,
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.begin_use = amdgpu_vce_ring_begin_use,
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.end_use = amdgpu_vce_ring_end_use,
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};
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static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev)
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{
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int i;
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for (i = 0; i < adev->vce.num_rings; i++)
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adev->vce.ring[i].funcs = &vce_v3_0_ring_funcs;
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if (adev->asic_type >= CHIP_STONEY) {
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for (i = 0; i < adev->vce.num_rings; i++)
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adev->vce.ring[i].funcs = &vce_v3_0_ring_vm_funcs;
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DRM_INFO("VCE enabled in VM mode\n");
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} else {
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for (i = 0; i < adev->vce.num_rings; i++)
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adev->vce.ring[i].funcs = &vce_v3_0_ring_phys_funcs;
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DRM_INFO("VCE enabled in physical mode\n");
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}
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}
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static const struct amdgpu_irq_src_funcs vce_v3_0_irq_funcs = {
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@ -369,4 +369,8 @@
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#define VCE_CMD_IB_AUTO 0x00000005
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#define VCE_CMD_SEMAPHORE 0x00000006
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#define VCE_CMD_IB_VM 0x00000102
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#define VCE_CMD_WAIT_GE 0x00000106
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#define VCE_CMD_UPDATE_PTB 0x00000107
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#define VCE_CMD_FLUSH_TLB 0x00000108
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#endif
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