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drm/amd/display: pass pipe_ctx straight to blank_pixel_data
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2063,12 +2063,13 @@ static void update_dchubp_dpp(
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static void dcn10_blank_pixel_data(
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struct dc *dc,
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struct stream_resource *stream_res,
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struct dc_stream_state *stream,
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struct pipe_ctx *pipe_ctx,
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bool blank)
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{
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enum dc_color_space color_space;
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struct tg_color black_color = {0};
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struct stream_resource *stream_res = &pipe_ctx->stream_res;
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struct dc_stream_state *stream = pipe_ctx->stream;
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/* program otg blank color */
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color_space = stream->output_color_space;
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@ -2127,8 +2128,7 @@ static void program_all_pipe_in_tree(
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pipe_ctx->stream_res.tg->funcs->program_global_sync(
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pipe_ctx->stream_res.tg);
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dc->hwss.blank_pixel_data(dc, &pipe_ctx->stream_res,
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pipe_ctx->stream, blank);
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dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
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}
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if (pipe_ctx->plane_state != NULL) {
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@ -2247,7 +2247,7 @@ static void dcn10_apply_ctx_for_surface(
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if (num_planes == 0) {
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/* OTG blank before remove all front end */
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dc->hwss.blank_pixel_data(dc, &top_pipe_to_program->stream_res, top_pipe_to_program->stream, true);
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dc->hwss.blank_pixel_data(dc, top_pipe_to_program, true);
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}
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/* Disconnect unused mpcc */
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@ -160,8 +160,7 @@ struct hw_sequencer_funcs {
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bool lock);
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void (*blank_pixel_data)(
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struct dc *dc,
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struct stream_resource *stream_res,
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struct dc_stream_state *stream,
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struct pipe_ctx *pipe_ctx,
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bool blank);
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void (*set_bandwidth)(
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