mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-24 17:40:53 +07:00
[BNX2]: Optimize firmware loading.
This is a follow up to the patches from Denys Vlasenkos <vda.linux@googlemail.com> to further optimize firmware loading. 1. In bnx2_init_cpus(), we allocate memory for decompression once and use it repeatedly instead of doing this for every firmware image. 2. We eliminate the BSS and SBSS firmware sections in bnx2_fw*.h since these are always zeros. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Michael Chan
David S. Miller
parent
dad8c73796
commit
ea1f8d5c3a
@ -2810,21 +2810,16 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
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/* Load the Text area. */
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offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
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if (fw->gz_text) {
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u32 *text;
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int j;
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text = vmalloc(FW_BUF_SIZE);
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if (!text)
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return -ENOMEM;
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rc = zlib_inflate_blob(text, FW_BUF_SIZE, fw->gz_text, fw->gz_text_len);
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if (rc < 0) {
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vfree(text);
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rc = zlib_inflate_blob(fw->text, FW_BUF_SIZE, fw->gz_text,
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fw->gz_text_len);
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if (rc < 0)
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return rc;
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}
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for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
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REG_WR_IND(bp, offset, cpu_to_le32(text[j]));
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REG_WR_IND(bp, offset, cpu_to_le32(fw->text[j]));
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}
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vfree(text);
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}
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/* Load the Data area. */
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@ -2839,21 +2834,21 @@ load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
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/* Load the SBSS area. */
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offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
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if (fw->sbss) {
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if (fw->sbss_len) {
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int j;
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for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
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REG_WR_IND(bp, offset, fw->sbss[j]);
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REG_WR_IND(bp, offset, 0);
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}
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}
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/* Load the BSS area. */
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offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
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if (fw->bss) {
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if (fw->bss_len) {
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int j;
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for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
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REG_WR_IND(bp, offset, fw->bss[j]);
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REG_WR_IND(bp, offset, 0);
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}
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}
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@ -2894,19 +2889,16 @@ bnx2_init_cpus(struct bnx2 *bp)
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if (!text)
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return -ENOMEM;
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rc = zlib_inflate_blob(text, FW_BUF_SIZE, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1));
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if (rc < 0) {
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vfree(text);
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if (rc < 0)
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goto init_cpu_err;
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}
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load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC1);
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rc = zlib_inflate_blob(text, FW_BUF_SIZE, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2));
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if (rc < 0) {
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vfree(text);
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if (rc < 0)
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goto init_cpu_err;
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}
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load_rv2p_fw(bp, text, rc /* == len */, RV2P_PROC2);
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vfree(text);
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/* Initialize the RX Processor. */
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cpu_reg.mode = BNX2_RXP_CPU_MODE;
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@ -2927,6 +2919,7 @@ bnx2_init_cpus(struct bnx2 *bp)
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else
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fw = &bnx2_rxp_fw_06;
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fw->text = text;
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rc = load_cpu_fw(bp, &cpu_reg, fw);
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if (rc)
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goto init_cpu_err;
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@ -2950,6 +2943,7 @@ bnx2_init_cpus(struct bnx2 *bp)
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else
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fw = &bnx2_txp_fw_06;
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fw->text = text;
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rc = load_cpu_fw(bp, &cpu_reg, fw);
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if (rc)
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goto init_cpu_err;
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@ -2973,6 +2967,7 @@ bnx2_init_cpus(struct bnx2 *bp)
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else
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fw = &bnx2_tpat_fw_06;
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fw->text = text;
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rc = load_cpu_fw(bp, &cpu_reg, fw);
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if (rc)
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goto init_cpu_err;
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@ -2996,6 +2991,7 @@ bnx2_init_cpus(struct bnx2 *bp)
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else
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fw = &bnx2_com_fw_06;
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fw->text = text;
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rc = load_cpu_fw(bp, &cpu_reg, fw);
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if (rc)
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goto init_cpu_err;
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@ -3017,11 +3013,13 @@ bnx2_init_cpus(struct bnx2 *bp)
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if (CHIP_NUM(bp) == CHIP_NUM_5709) {
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fw = &bnx2_cp_fw_09;
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fw->text = text;
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rc = load_cpu_fw(bp, &cpu_reg, fw);
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if (rc)
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goto init_cpu_err;
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}
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init_cpu_err:
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vfree(text);
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return rc;
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}
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@ -6738,7 +6738,7 @@ struct fw_info {
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const u32 text_addr;
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const u32 text_len;
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const u32 text_index;
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/* u32 *text;*/
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u32 *text;
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u8 *gz_text;
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const u32 gz_text_len;
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@ -6752,13 +6752,11 @@ struct fw_info {
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const u32 sbss_addr;
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const u32 sbss_len;
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const u32 sbss_index;
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const u32 *sbss;
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/* BSS section. */
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const u32 bss_addr;
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const u32 bss_len;
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const u32 bss_index;
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const u32 *bss;
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/* Read-only section. */
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const u32 rodata_addr;
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@ -1048,8 +1048,6 @@ static const u32 bnx2_COM_b06FwRodata[(0x88/4) + 1] = {
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0x08002bd8, 0x08002c08, 0x08002c38, 0x00000000, 0x080060cc, 0x080060cc,
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0x080060cc, 0x080060cc, 0x080060cc, 0x08006100, 0x08006100, 0x08006140,
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0x0800614c, 0x0800614c, 0x080060cc, 0x00000000, 0x00000000 };
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static const u32 bnx2_COM_b06FwBss[(0x88/4) + 1] = { 0x0 };
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static const u32 bnx2_COM_b06FwSbss[(0x60/4) + 1] = { 0x0 };
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static struct fw_info bnx2_com_fw_06 = {
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.ver_major = 0x3,
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@ -1072,12 +1070,10 @@ static struct fw_info bnx2_com_fw_06 = {
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.sbss_addr = 0x08007e00,
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.sbss_len = 0x60,
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.sbss_index = 0x0,
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.sbss = bnx2_COM_b06FwSbss,
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.bss_addr = 0x08007e60,
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.bss_len = 0x88,
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.bss_index = 0x0,
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.bss = bnx2_COM_b06FwBss,
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.rodata_addr = 0x08007d58,
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.rodata_len = 0x88,
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@ -1762,9 +1758,6 @@ static u32 bnx2_RXP_b06FwRodata[(0x278/4) + 1] = {
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0x08006030, 0x08006030, 0x08006018, 0x08006030, 0x08006030, 0x08006030,
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0x08006024, 0x00000000, 0x00000000 };
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static u32 bnx2_RXP_b06FwBss[(0x13dc/4) + 1] = { 0x0 };
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static u32 bnx2_RXP_b06FwSbss[(0x2c/4) + 1] = { 0x0 };
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static struct fw_info bnx2_rxp_fw_06 = {
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.ver_major = 0x2,
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.ver_minor = 0x8,
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@ -1786,12 +1779,10 @@ static struct fw_info bnx2_rxp_fw_06 = {
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.sbss_addr = 0x080069c0,
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.sbss_len = 0x2c,
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.sbss_index = 0x0,
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.sbss = bnx2_RXP_b06FwSbss,
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.bss_addr = 0x080069f0,
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.bss_len = 0x13dc,
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.bss_index = 0x0,
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.bss = bnx2_RXP_b06FwBss,
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.rodata_addr = 0x08006728,
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.rodata_len = 0x278,
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@ -2257,8 +2248,6 @@ static u8 bnx2_TPAT_b06FwText[] = {
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static u32 bnx2_TPAT_b06FwData[(0x0/4) + 1] = { 0x0 };
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static u32 bnx2_TPAT_b06FwRodata[(0x0/4) + 1] = { 0x0 };
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static u32 bnx2_TPAT_b06FwBss[(0x250/4) + 1] = { 0x0 };
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static u32 bnx2_TPAT_b06FwSbss[(0x34/4) + 1] = { 0x0 };
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static struct fw_info bnx2_tpat_fw_06 = {
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.ver_major = 0x1,
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@ -2281,12 +2270,10 @@ static struct fw_info bnx2_tpat_fw_06 = {
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.sbss_addr = 0x08001a60,
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.sbss_len = 0x34,
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.sbss_index = 0x0,
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.sbss = bnx2_TPAT_b06FwSbss,
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.bss_addr = 0x08001aa0,
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.bss_len = 0x250,
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.bss_index = 0x0,
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.bss = bnx2_TPAT_b06FwBss,
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.rodata_addr = 0x00000000,
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.rodata_len = 0x0,
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@ -2714,8 +2701,6 @@ static u8 bnx2_TXP_b06FwText[] = {
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static u32 bnx2_TXP_b06FwData[(0x0/4) + 1] = { 0x0 };
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static u32 bnx2_TXP_b06FwRodata[(0x0/4) + 1] = { 0x0 };
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static u32 bnx2_TXP_b06FwBss[(0x1c4/4) + 1] = { 0x0 };
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static u32 bnx2_TXP_b06FwSbss[(0x38/4) + 1] = { 0x0 };
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static struct fw_info bnx2_txp_fw_06 = {
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.ver_major = 0x1,
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@ -2738,12 +2723,10 @@ static struct fw_info bnx2_txp_fw_06 = {
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.sbss_addr = 0x08005760,
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.sbss_len = 0x38,
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.sbss_index = 0x0,
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.sbss = bnx2_TXP_b06FwSbss,
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.bss_addr = 0x080057a0,
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.bss_len = 0x1c4,
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.bss_index = 0x0,
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.bss = bnx2_TXP_b06FwBss,
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.rodata_addr = 0x00000000,
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.rodata_len = 0x0,
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@ -1046,8 +1046,6 @@ static const u32 bnx2_COM_b09FwRodata[(0x88/4) + 1] = {
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0x08002b3c, 0x08002b6c, 0x08002b9c, 0x00000000, 0x0800604c, 0x0800604c,
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0x0800604c, 0x0800604c, 0x0800604c, 0x08006078, 0x08006078, 0x080060b8,
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0x080060c4, 0x080060c4, 0x0800604c, 0x00000000, 0x00000000 };
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static const u32 bnx2_COM_b09FwBss[(0x88/4) + 1] = { 0x0 };
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static const u32 bnx2_COM_b09FwSbss[(0x60/4) + 1] = { 0x0 };
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static struct fw_info bnx2_com_fw_09 = {
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.ver_major = 0x3,
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@ -1070,12 +1068,10 @@ static struct fw_info bnx2_com_fw_09 = {
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.sbss_addr = 0x08007e60,
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.sbss_len = 0x60,
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.sbss_index = 0x0,
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.sbss = bnx2_COM_b09FwSbss,
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.bss_addr = 0x08007ec0,
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.bss_len = 0x88,
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.bss_index = 0x0,
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.bss = bnx2_COM_b09FwBss,
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.rodata_addr = 0x08007dc0,
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.rodata_len = 0x88,
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@ -2243,8 +2239,6 @@ static const u32 bnx2_CP_b09FwRodata[(0x118/4) + 1] = {
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0x080032e8, 0x08003300, 0x08003320, 0x08003358, 0x08003338, 0x08003338,
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0x080050d4, 0x080050d4, 0x080050d4, 0x080050d4, 0x080050d4, 0x080050fc,
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0x080050fc, 0x08005124, 0x08005174, 0x08005144, 0x00000000 };
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static const u32 bnx2_CP_b09FwBss[(0x3b0/4) + 1] = { 0x0 };
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static const u32 bnx2_CP_b09FwSbss[(0xa1/4) + 1] = { 0x0 };
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static struct fw_info bnx2_cp_fw_09 = {
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.ver_major = 0x3,
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@ -2267,12 +2261,10 @@ static struct fw_info bnx2_cp_fw_09 = {
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.sbss_addr = 0x08007024,
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.sbss_len = 0xa1,
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.sbss_index = 0x0,
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.sbss = bnx2_CP_b09FwSbss,
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.bss_addr = 0x080070d0,
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.bss_len = 0x3b0,
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.bss_index = 0x0,
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.bss = bnx2_CP_b09FwBss,
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.rodata_addr = 0x08006ee8,
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.rodata_len = 0x118,
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@ -2953,8 +2945,6 @@ static const u32 bnx2_RXP_b09FwRodata[(0x278/4) + 1] = {
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0x08006058, 0x08006070, 0x08006070, 0x08006070, 0x08006058, 0x08006070,
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0x08006070, 0x08006070, 0x08006058, 0x08006070, 0x08006070, 0x08006070,
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0x08006064, 0x00000000, 0x00000000 };
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static const u32 bnx2_RXP_b09FwBss[(0x13dc/4) + 1] = { 0x0 };
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static const u32 bnx2_RXP_b09FwSbss[(0x20/4) + 1] = { 0x0 };
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static struct fw_info bnx2_rxp_fw_09 = {
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.ver_major = 0x3,
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@ -2977,12 +2967,10 @@ static struct fw_info bnx2_rxp_fw_09 = {
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.sbss_addr = 0x08006a00,
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.sbss_len = 0x20,
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.sbss_index = 0x0,
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.sbss = bnx2_RXP_b09FwSbss,
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.bss_addr = 0x08006a20,
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.bss_len = 0x13dc,
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.bss_index = 0x0,
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.bss = bnx2_RXP_b09FwBss,
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.rodata_addr = 0x08006768,
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.rodata_len = 0x278,
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@ -3245,8 +3233,6 @@ static u8 bnx2_TPAT_b09FwText[] = {
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static const u32 bnx2_TPAT_b09FwData[(0x0/4) + 1] = { 0x0 };
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static const u32 bnx2_TPAT_b09FwRodata[(0x0/4) + 1] = { 0x0 };
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static const u32 bnx2_TPAT_b09FwBss[(0x850/4) + 1] = { 0x0 };
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static const u32 bnx2_TPAT_b09FwSbss[(0x2c/4) + 1] = { 0x0 };
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static struct fw_info bnx2_tpat_fw_09 = {
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.ver_major = 0x3,
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@ -3269,12 +3255,10 @@ static struct fw_info bnx2_tpat_fw_09 = {
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.sbss_addr = 0x08002088,
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.sbss_len = 0x2c,
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.sbss_index = 0x0,
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.sbss = bnx2_TPAT_b09FwSbss,
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.bss_addr = 0x080020c0,
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.bss_len = 0x850,
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.bss_index = 0x0,
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.bss = bnx2_TPAT_b09FwBss,
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.rodata_addr = 0x00000000,
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.rodata_len = 0x0,
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@ -4060,8 +4044,6 @@ static const u32 bnx2_TXP_b09FwRodata[(0x30/4) + 1] = {
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0x08004060, 0x0800408c, 0x080040d4, 0x080040d4, 0x08003f60, 0x08003f8c,
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0x08003f8c, 0x080040d4, 0x080040d4, 0x080040d4, 0x08003ff4, 0x00000000,
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0x00000000 };
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static const u32 bnx2_TXP_b09FwBss[(0xa20/4) + 1] = { 0x0 };
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static const u32 bnx2_TXP_b09FwSbss[(0x8c/4) + 1] = { 0x0 };
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static struct fw_info bnx2_txp_fw_09 = {
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.ver_major = 0x3,
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@ -4084,12 +4066,10 @@ static struct fw_info bnx2_txp_fw_09 = {
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.sbss_addr = 0x08004750,
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.sbss_len = 0x8c,
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.sbss_index = 0x0,
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.sbss = bnx2_TXP_b09FwSbss,
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.bss_addr = 0x080047e0,
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.bss_len = 0xa20,
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.bss_index = 0x0,
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.bss = bnx2_TXP_b09FwBss,
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.rodata_addr = 0x08004638,
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.rodata_len = 0x30,
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