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drm/amd/display: Clean up DCN cursor code
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -776,27 +776,6 @@ void hubp1_read_state(struct dcn10_hubp *hubp1,
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QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);
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}
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bool hubp1_cursor_program_control(
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struct dcn10_hubp *hubp1,
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bool pixel_data_invert,
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enum dc_cursor_color_format color_format)
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{
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if (REG(CURSOR_SETTINS))
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REG_SET_2(CURSOR_SETTINS, 0,
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/* no shift of the cursor HDL schedule */
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CURSOR0_DST_Y_OFFSET, 0,
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/* used to shift the cursor chunk request deadline */
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CURSOR0_CHUNK_HDL_ADJUST, 3);
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else
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REG_SET_2(CURSOR_SETTINGS, 0,
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/* no shift of the cursor HDL schedule */
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CURSOR0_DST_Y_OFFSET, 0,
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/* used to shift the cursor chunk request deadline */
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CURSOR0_CHUNK_HDL_ADJUST, 3);
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return true;
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}
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enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch)
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{
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enum cursor_pitch hw_pitch;
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@ -866,9 +845,11 @@ void hubp1_cursor_set_attributes(
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CURSOR_PITCH, hw_pitch,
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CURSOR_LINES_PER_CHUNK, lpc);
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hubp1_cursor_program_control(hubp1,
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attr->attribute_flags.bits.INVERT_PIXEL_DATA,
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attr->color_format);
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REG_SET_2(CURSOR_SETTINS, 0,
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/* no shift of the cursor HDL schedule */
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CURSOR0_DST_Y_OFFSET, 0,
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/* used to shift the cursor chunk request deadline */
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CURSOR0_CHUNK_HDL_ADJUST, 3);
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}
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void hubp1_cursor_set_position(
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@ -683,9 +683,4 @@ void hubp1_read_state(struct dcn10_hubp *hubp1,
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enum cursor_pitch hubp1_get_cursor_pitch(unsigned int pitch);
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bool hubp1_cursor_program_control(
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struct dcn10_hubp *hubp1,
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bool pixel_data_invert,
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enum dc_cursor_color_format color_format);
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#endif
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