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clk: qoriq: Add ls1043a support.
Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Scott Wood <scottwood@freescale.com>
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@ -244,6 +244,28 @@ static const struct clockgen_muxinfo clockgen2_cmux_cgb = {
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},
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};
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static const struct clockgen_muxinfo ls1043a_hwa1 = {
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{
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{},
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{},
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{ CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
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{ CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
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{},
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{},
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{ CLKSEL_VALID, CGA_PLL2, PLL_DIV2 },
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{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
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},
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};
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static const struct clockgen_muxinfo ls1043a_hwa2 = {
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{
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{},
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{ CLKSEL_VALID, CGA_PLL2, PLL_DIV1 },
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{},
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{ CLKSEL_VALID, CGA_PLL2, PLL_DIV3 },
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},
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};
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static const struct clockgen_muxinfo t1023_hwa1 = {
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{
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{},
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@ -451,6 +473,21 @@ static const struct clockgen_chipinfo chipinfo[] = {
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},
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.pll_mask = 0x03,
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},
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{
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.compat = "fsl,ls1043a-clockgen",
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.init_periph = t2080_init_periph,
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.cmux_groups = {
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&t1040_cmux
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},
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.hwaccel = {
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&ls1043a_hwa1, &ls1043a_hwa2
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},
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.cmux_to_group = {
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0, -1
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},
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.pll_mask = 0x07,
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.flags = CG_PLL_8BIT,
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},
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{
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.compat = "fsl,ls2080a-clockgen",
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.cmux_groups = {
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@ -1227,6 +1264,7 @@ static void __init clockgen_init(struct device_node *np)
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CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init);
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CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init);
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CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init);
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CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init);
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CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init);
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/* Legacy nodes */
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