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Some small fixes for the new sunxi clk driver introduced this merge window.

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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fixes from Stephen Boyd:
 "Some small fixes for the new sunxi clk driver introduced this merge
  window"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: sunxi-ng: Fix wrong reset register offsets
  clk: sunxi-ng: nk: Make ccu_nk_find_best static
  clk: sunxi-ng: Fix inverted test condition in ccu_helper_wait_for_lock
  clk: sunxi: Fix return value check in sun8i_a23_mbus_setup()
  clk: sunxi: pll2: Fix return value check in sun4i_pll2_setup()
This commit is contained in:
Linus Torvalds 2016-09-12 14:49:21 -07:00
commit e8988e0550
4 changed files with 14 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
drivers/clk/sunxi-ng/ccu-sun8i-h3.c
View File

@ -783,14 +783,14 @@ static struct ccu_reset_map sun8i_h3_ccu_resets[] = {
[RST_BUS_I2S1] = { 0x2d0, BIT(13) },
[RST_BUS_I2S2] = { 0x2d0, BIT(14) },
[RST_BUS_I2C0] = { 0x2d4, BIT(0) },
[RST_BUS_I2C1] = { 0x2d4, BIT(1) },
[RST_BUS_I2C2] = { 0x2d4, BIT(2) },
[RST_BUS_UART0] = { 0x2d4, BIT(16) },
[RST_BUS_UART1] = { 0x2d4, BIT(17) },
[RST_BUS_UART2] = { 0x2d4, BIT(18) },
[RST_BUS_UART3] = { 0x2d4, BIT(19) },
[RST_BUS_SCR] = { 0x2d4, BIT(20) },
[RST_BUS_I2C0] = { 0x2d8, BIT(0) },
[RST_BUS_I2C1] = { 0x2d8, BIT(1) },
[RST_BUS_I2C2] = { 0x2d8, BIT(2) },
[RST_BUS_UART0] = { 0x2d8, BIT(16) },
[RST_BUS_UART1] = { 0x2d8, BIT(17) },
[RST_BUS_UART2] = { 0x2d8, BIT(18) },
[RST_BUS_UART3] = { 0x2d8, BIT(19) },
[RST_BUS_SCR] = { 0x2d8, BIT(20) },
};
static const struct sunxi_ccu_desc sun8i_h3_ccu_desc = {

6
drivers/clk/sunxi-ng/ccu_nk.c
View File

@ -14,9 +14,9 @@
#include "ccu_gate.h"
#include "ccu_nk.h"
void ccu_nk_find_best(unsigned long parent, unsigned long rate,
unsigned int max_n, unsigned int max_k,
unsigned int *n, unsigned int *k)
static void ccu_nk_find_best(unsigned long parent, unsigned long rate,
unsigned int max_n, unsigned int max_k,
unsigned int *n, unsigned int *k)
{
unsigned long best_rate = 0;
unsigned int best_k = 0, best_n = 0;

4
drivers/clk/sunxi/clk-a10-pll2.c
View File

@ -73,7 +73,7 @@ static void __init sun4i_pll2_setup(struct device_node *node,
SUN4I_PLL2_PRE_DIV_WIDTH,
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
&sun4i_a10_pll2_lock);
if (!prediv_clk) {
if (IS_ERR(prediv_clk)) {
pr_err("Couldn't register the prediv clock\n");
goto err_free_array;
}
@ -106,7 +106,7 @@ static void __init sun4i_pll2_setup(struct device_node *node,
&mult->hw, &clk_multiplier_ops,
&gate->hw, &clk_gate_ops,
CLK_SET_RATE_PARENT);
if (!base_clk) {
if (IS_ERR(base_clk)) {
pr_err("Couldn't register the base multiplier clock\n");
goto err_free_multiplier;
}

2
drivers/clk/sunxi/clk-sun8i-mbus.c
View File

@ -48,7 +48,7 @@ static void __init sun8i_a23_mbus_setup(struct device_node *node)
return;
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
if (!reg) {
if (IS_ERR(reg)) {
pr_err("Could not get registers for sun8i-mbus-clk\n");
goto err_free_parents;
}