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clk: exynos5410: register clocks using common clock framework
The EXYNOS5410 clocks are statically listed and registered using the Samsung specific common clock helper functions. Signed-off-by: Tarek Dakhran <t.dakhran@samsung.com> Signed-off-by: Vyacheslav Tyrtov <v.tyrtov@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This commit is contained in:
Tarek Dakhran
Kukjin Kim
parent
bfed1074f2
commit
e7ef0b632e
45
Documentation/devicetree/bindings/clock/exynos5410-clock.txt
Normal file
45
Documentation/devicetree/bindings/clock/exynos5410-clock.txt
Normal file
@ -0,0 +1,45 @@
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* Samsung Exynos5410 Clock Controller
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The Exynos5410 clock controller generates and supplies clock to various
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controllers within the Exynos5410 SoC.
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Required Properties:
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- compatible: should be "samsung,exynos5410-clock"
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- reg: physical base address of the controller and length of memory mapped
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region.
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- #clock-cells: should be 1.
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All available clocks are defined as preprocessor macros in
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dt-bindings/clock/exynos5410.h header and can be used in device
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tree sources.
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External clock:
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There is clock that is generated outside the SoC. It
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is expected that it is defined using standard clock bindings
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with following clock-output-name:
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- "fin_pll" - PLL input clock from XXTI
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Example 1: An example of a clock controller node is listed below.
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clock: clock-controller@0x10010000 {
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compatible = "samsung,exynos5410-clock";
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reg = <0x10010000 0x30000>;
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#clock-cells = <1>;
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};
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Example 2: UART controller node that consumes the clock generated by the clock
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controller. Refer to the standard clock bindings for information
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about 'clocks' and 'clock-names' property.
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serial@12C20000 {
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compatible = "samsung,exynos4210-uart";
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reg = <0x12C00000 0x100>;
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interrupts = <0 51 0>;
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clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
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clock-names = "uart", "clk_uart_baud0";
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};
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@ -7,6 +7,7 @@ obj-$(CONFIG_SOC_EXYNOS3250) += clk-exynos3250.o
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obj-$(CONFIG_ARCH_EXYNOS4) += clk-exynos4.o
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obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
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obj-$(CONFIG_SOC_EXYNOS5260) += clk-exynos5260.o
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obj-$(CONFIG_SOC_EXYNOS5410) += clk-exynos5410.o
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obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
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obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
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obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
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209
drivers/clk/samsung/clk-exynos5410.c
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209
drivers/clk/samsung/clk-exynos5410.c
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@ -0,0 +1,209 @@
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/*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* Author: Tarek Dakhran <t.dakhran@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Common Clock Framework support for Exynos5410 SoC.
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*/
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#include <dt-bindings/clock/exynos5410.h>
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#include <linux/clk.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include "clk.h"
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#define APLL_LOCK 0x0
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#define APLL_CON0 0x100
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#define CPLL_LOCK 0x10020
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#define CPLL_CON0 0x10120
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#define MPLL_LOCK 0x4000
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#define MPLL_CON0 0x4100
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#define BPLL_LOCK 0x20010
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#define BPLL_CON0 0x20110
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#define KPLL_LOCK 0x28000
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#define KPLL_CON0 0x28100
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#define SRC_CPU 0x200
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#define DIV_CPU0 0x500
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#define SRC_CPERI1 0x4204
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#define DIV_TOP0 0x10510
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#define DIV_TOP1 0x10514
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#define DIV_FSYS1 0x1054c
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#define DIV_FSYS2 0x10550
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#define DIV_PERIC0 0x10558
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#define SRC_TOP0 0x10210
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#define SRC_TOP1 0x10214
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#define SRC_TOP2 0x10218
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#define SRC_FSYS 0x10244
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#define SRC_PERIC0 0x10250
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#define SRC_MASK_FSYS 0x10340
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#define SRC_MASK_PERIC0 0x10350
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#define GATE_BUS_FSYS0 0x10740
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#define GATE_IP_FSYS 0x10944
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#define GATE_IP_PERIC 0x10950
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#define GATE_IP_PERIS 0x10960
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#define SRC_CDREX 0x20200
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#define SRC_KFC 0x28200
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#define DIV_KFC0 0x28500
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/* list of PLLs */
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enum exynos5410_plls {
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apll, cpll, mpll,
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bpll, kpll,
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nr_plls /* number of PLLs */
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};
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/* list of all parent clocks */
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PNAME(apll_p) = { "fin_pll", "fout_apll", };
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PNAME(bpll_p) = { "fin_pll", "fout_bpll", };
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PNAME(cpll_p) = { "fin_pll", "fout_cpll" };
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PNAME(mpll_p) = { "fin_pll", "fout_mpll", };
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PNAME(kpll_p) = { "fin_pll", "fout_kpll", };
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PNAME(mout_cpu_p) = { "mout_apll", "sclk_mpll", };
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PNAME(mout_kfc_p) = { "mout_kpll", "sclk_mpll", };
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PNAME(mpll_user_p) = { "fin_pll", "sclk_mpll", };
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PNAME(bpll_user_p) = { "fin_pll", "sclk_bpll", };
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PNAME(mpll_bpll_p) = { "sclk_mpll_muxed", "sclk_bpll_muxed", };
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PNAME(group2_p) = { "fin_pll", "fin_pll", "none", "none",
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"none", "none", "sclk_mpll_bpll",
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"none", "none", "sclk_cpll" };
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static struct samsung_mux_clock exynos5410_mux_clks[] __initdata = {
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MUX(0, "mout_apll", apll_p, SRC_CPU, 0, 1),
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MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
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MUX(0, "mout_kpll", kpll_p, SRC_KFC, 0, 1),
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MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
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MUX(0, "sclk_mpll", mpll_p, SRC_CPERI1, 8, 1),
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MUX(0, "sclk_mpll_muxed", mpll_user_p, SRC_TOP2, 20, 1),
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MUX(0, "sclk_bpll", bpll_p, SRC_CDREX, 0, 1),
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MUX(0, "sclk_bpll_muxed", bpll_user_p, SRC_TOP2, 24, 1),
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MUX(0, "sclk_cpll", cpll_p, SRC_TOP2, 8, 1),
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MUX(0, "sclk_mpll_bpll", mpll_bpll_p, SRC_TOP1, 20, 1),
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MUX(0, "mout_mmc0", group2_p, SRC_FSYS, 0, 4),
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MUX(0, "mout_mmc1", group2_p, SRC_FSYS, 4, 4),
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MUX(0, "mout_mmc2", group2_p, SRC_FSYS, 8, 4),
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MUX(0, "mout_uart0", group2_p, SRC_PERIC0, 0, 4),
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MUX(0, "mout_uart1", group2_p, SRC_PERIC0, 4, 4),
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MUX(0, "mout_uart2", group2_p, SRC_PERIC0, 8, 4),
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MUX(0, "mout_aclk200", mpll_bpll_p, SRC_TOP0, 12, 1),
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MUX(0, "mout_aclk400", mpll_bpll_p, SRC_TOP0, 20, 1),
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};
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static struct samsung_div_clock exynos5410_div_clks[] __initdata = {
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DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
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DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),
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DIV(0, "div_acp", "div_arm2", DIV_CPU0, 8, 3),
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DIV(0, "div_cpud", "div_arm2", DIV_CPU0, 4, 3),
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DIV(0, "div_atb", "div_arm2", DIV_CPU0, 16, 3),
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DIV(0, "pclk_dbg", "div_arm2", DIV_CPU0, 20, 3),
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DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
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DIV(0, "div_aclk", "div_kfc", DIV_KFC0, 4, 3),
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DIV(0, "div_pclk", "div_kfc", DIV_KFC0, 20, 3),
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DIV(0, "aclk66_pre", "sclk_mpll_muxed", DIV_TOP1, 24, 3),
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DIV(0, "aclk66", "aclk66_pre", DIV_TOP0, 0, 3),
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DIV(0, "div_mmc0", "mout_mmc0", DIV_FSYS1, 0, 4),
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DIV(0, "div_mmc1", "mout_mmc1", DIV_FSYS1, 16, 4),
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DIV(0, "div_mmc2", "mout_mmc2", DIV_FSYS2, 0, 4),
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DIV_F(0, "div_mmc_pre0", "div_mmc0",
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DIV_FSYS1, 8, 8, CLK_SET_RATE_PARENT, 0),
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DIV_F(0, "div_mmc_pre1", "div_mmc1",
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DIV_FSYS1, 24, 8, CLK_SET_RATE_PARENT, 0),
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DIV_F(0, "div_mmc_pre2", "div_mmc2",
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DIV_FSYS2, 8, 8, CLK_SET_RATE_PARENT, 0),
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DIV(0, "div_uart0", "mout_uart0", DIV_PERIC0, 0, 4),
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DIV(0, "div_uart1", "mout_uart1", DIV_PERIC0, 4, 4),
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DIV(0, "div_uart2", "mout_uart2", DIV_PERIC0, 8, 4),
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DIV(0, "div_uart3", "mout_uart3", DIV_PERIC0, 12, 4),
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DIV(0, "aclk200", "mout_aclk200", DIV_TOP0, 12, 3),
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DIV(0, "aclk400", "mout_aclk400", DIV_TOP0, 24, 3),
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};
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static struct samsung_gate_clock exynos5410_gate_clks[] __initdata = {
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GATE(CLK_MCT, "mct", "aclk66", GATE_IP_PERIS, 18, 0, 0),
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GATE(CLK_SCLK_MMC0, "sclk_mmc0", "div_mmc_pre0",
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SRC_MASK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_MMC1, "sclk_mmc1", "div_mmc_pre1",
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SRC_MASK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_MMC2, "sclk_mmc2", "div_mmc_pre2",
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SRC_MASK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_MMC0, "sdmmc0", "aclk200", GATE_BUS_FSYS0, 12, 0, 0),
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GATE(CLK_MMC1, "sdmmc1", "aclk200", GATE_BUS_FSYS0, 13, 0, 0),
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GATE(CLK_MMC2, "sdmmc2", "aclk200", GATE_BUS_FSYS0, 14, 0, 0),
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GATE(CLK_UART0, "uart0", "aclk66", GATE_IP_PERIC, 0, 0, 0),
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GATE(CLK_UART1, "uart1", "aclk66", GATE_IP_PERIC, 1, 0, 0),
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GATE(CLK_UART2, "uart2", "aclk66", GATE_IP_PERIC, 2, 0, 0),
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GATE(CLK_SCLK_UART0, "sclk_uart0", "div_uart0",
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SRC_MASK_PERIC0, 0, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_UART1, "sclk_uart1", "div_uart1",
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SRC_MASK_PERIC0, 4, CLK_SET_RATE_PARENT, 0),
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GATE(CLK_SCLK_UART2, "sclk_uart2", "div_uart2",
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SRC_MASK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
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};
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static struct samsung_pll_clock exynos5410_plls[nr_plls] __initdata = {
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[apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
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APLL_CON0, NULL),
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[cpll] = PLL(pll_35xx, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
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CPLL_CON0, NULL),
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[mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
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MPLL_CON0, NULL),
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[bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
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BPLL_CON0, NULL),
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[kpll] = PLL(pll_35xx, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
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KPLL_CON0, NULL),
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};
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/* register exynos5410 clocks */
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static void __init exynos5410_clk_init(struct device_node *np)
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{
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struct samsung_clk_provider *ctx;
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void __iomem *reg_base;
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reg_base = of_iomap(np, 0);
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if (!reg_base)
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panic("%s: failed to map registers\n", __func__);
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ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
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samsung_clk_register_pll(ctx, exynos5410_plls,
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ARRAY_SIZE(exynos5410_plls), reg_base);
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samsung_clk_register_mux(ctx, exynos5410_mux_clks,
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ARRAY_SIZE(exynos5410_mux_clks));
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samsung_clk_register_div(ctx, exynos5410_div_clks,
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ARRAY_SIZE(exynos5410_div_clks));
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samsung_clk_register_gate(ctx, exynos5410_gate_clks,
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ARRAY_SIZE(exynos5410_gate_clks));
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pr_debug("Exynos5410: clock setup completed.\n");
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}
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CLK_OF_DECLARE(exynos5410_clk, "samsung,exynos5410-clock", exynos5410_clk_init);
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33
include/dt-bindings/clock/exynos5410.h
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33
include/dt-bindings/clock/exynos5410.h
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@ -0,0 +1,33 @@
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#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5410_H
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#define _DT_BINDINGS_CLOCK_EXYNOS_5410_H
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/* core clocks */
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#define CLK_FIN_PLL 1
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#define CLK_FOUT_APLL 2
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#define CLK_FOUT_CPLL 3
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#define CLK_FOUT_MPLL 4
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#define CLK_FOUT_BPLL 5
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#define CLK_FOUT_KPLL 6
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/* gate for special clocks (sclk) */
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#define CLK_SCLK_UART0 128
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#define CLK_SCLK_UART1 129
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#define CLK_SCLK_UART2 130
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#define CLK_SCLK_UART3 131
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#define CLK_SCLK_MMC0 132
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#define CLK_SCLK_MMC1 133
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#define CLK_SCLK_MMC2 134
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/* gate clocks */
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#define CLK_UART0 257
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#define CLK_UART1 258
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#define CLK_UART2 259
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#define CLK_UART3 260
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#define CLK_MCT 315
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#define CLK_MMC0 351
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#define CLK_MMC1 352
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#define CLK_MMC2 353
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#define CLK_NR_CLKS 512
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */
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