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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-01-23 01:09:48 +07:00
vxge: Titan1A detection
Detect if the adapter is Titan or Titan1A, and tune the driver for this hardware. Also, remove unnecessary function __vxge_hw_device_id_get. Signed-off-by: Jon Mason <jon.mason@exar.com> Signed-off-by: Ram Vepa <ram.vepa@exar.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Jon Mason
David S. Miller
parent
c3150eac9f
commit
e7935c9669
@ -98,9 +98,6 @@ __vxge_hw_device_fifo_config_check(struct vxge_hw_fifo_config *fifo_config);
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static enum vxge_hw_status
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__vxge_hw_device_config_check(struct vxge_hw_device_config *new_config);
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static void
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__vxge_hw_device_id_get(struct __vxge_hw_device *hldev);
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static void
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__vxge_hw_device_host_info_get(struct __vxge_hw_device *hldev);
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@ -805,26 +802,6 @@ __vxge_hw_device_reg_addr_get(struct __vxge_hw_device *hldev)
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return status;
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}
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/*
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* __vxge_hw_device_id_get
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* This routine returns sets the device id and revision numbers into the device
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* structure
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*/
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void __vxge_hw_device_id_get(struct __vxge_hw_device *hldev)
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{
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u64 val64;
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val64 = readq(&hldev->common_reg->titan_asic_id);
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hldev->device_id =
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(u16)VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_DEVICE_ID(val64);
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hldev->major_revision =
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(u8)VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MAJOR_REVISION(val64);
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hldev->minor_revision =
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(u8)VXGE_HW_TITAN_ASIC_ID_GET_INITIAL_MINOR_REVISION(val64);
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}
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/*
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* __vxge_hw_device_access_rights_get: Get Access Rights of the driver
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* This routine returns the Access Rights of the driver
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@ -1327,7 +1304,6 @@ vxge_hw_device_initialize(
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vfree(hldev);
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goto exit;
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}
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__vxge_hw_device_id_get(hldev);
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__vxge_hw_device_host_info_get(hldev);
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@ -4442,16 +4418,18 @@ vxge_hw_vpath_open(struct __vxge_hw_device *hldev,
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void
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vxge_hw_vpath_rx_doorbell_init(struct __vxge_hw_vpath_handle *vp)
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{
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struct __vxge_hw_virtualpath *vpath = NULL;
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struct __vxge_hw_virtualpath *vpath = vp->vpath;
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struct __vxge_hw_ring *ring = vpath->ringh;
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struct vxgedev *vdev = netdev_priv(vpath->hldev->ndev);
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u64 new_count, val64, val164;
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struct __vxge_hw_ring *ring;
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vpath = vp->vpath;
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ring = vpath->ringh;
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if (vdev->titan1) {
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new_count = readq(&vpath->vp_reg->rxdmem_size);
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new_count &= 0x1fff;
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} else
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new_count = ring->config->ring_blocks * VXGE_HW_BLOCK_SIZE / 8;
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new_count = readq(&vpath->vp_reg->rxdmem_size);
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new_count &= 0x1fff;
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val164 = (VXGE_HW_RXDMEM_SIZE_PRC_RXDMEM_SIZE(new_count));
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val164 = VXGE_HW_RXDMEM_SIZE_PRC_RXDMEM_SIZE(new_count);
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writeq(VXGE_HW_PRC_RXD_DOORBELL_NEW_QW_CNT(val164),
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&vpath->vp_reg->prc_rxd_doorbell);
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@ -713,9 +713,6 @@ struct __vxge_hw_vpath_handle{
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/**
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* struct __vxge_hw_device - Hal device object
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* @magic: Magic Number
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* @device_id: PCI Device Id of the adapter
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* @major_revision: PCI Device major revision
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* @minor_revision: PCI Device minor revision
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* @bar0: BAR0 virtual address.
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* @pdev: Physical device handle
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* @config: Confguration passed by the LL driver at initialization
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@ -727,9 +724,6 @@ struct __vxge_hw_device {
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u32 magic;
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#define VXGE_HW_DEVICE_MAGIC 0x12345678
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#define VXGE_HW_DEVICE_DEAD 0xDEADDEAD
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u16 device_id;
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u8 major_revision;
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u8 minor_revision;
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void __iomem *bar0;
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struct pci_dev *pdev;
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struct net_device *ndev;
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@ -2012,8 +2012,23 @@ static int vxge_open_vpaths(struct vxgedev *vdev)
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for (i = 0; i < vdev->no_of_vpath; i++) {
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vpath = &vdev->vpaths[i];
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vxge_assert(vpath->is_configured);
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if (!vdev->titan1) {
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struct vxge_hw_vp_config *vcfg;
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vcfg = &vdev->devh->config.vp_config[vpath->device_id];
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vcfg->rti.urange_a = RTI_T1A_RX_URANGE_A;
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vcfg->rti.urange_b = RTI_T1A_RX_URANGE_B;
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vcfg->rti.urange_c = RTI_T1A_RX_URANGE_C;
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vcfg->tti.uec_a = TTI_T1A_TX_UFC_A;
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vcfg->tti.uec_b = TTI_T1A_TX_UFC_B;
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vcfg->tti.uec_c = TTI_T1A_TX_UFC_C(vdev->mtu);
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vcfg->tti.uec_d = TTI_T1A_TX_UFC_D(vdev->mtu);
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vcfg->tti.ltimer_val = VXGE_T1A_TTI_LTIMER_VAL;
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vcfg->tti.rtimer_val = VXGE_T1A_TTI_RTIMER_VAL;
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}
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attr.vp_id = vpath->device_id;
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attr.fifo_attr.callback = vxge_xmit_compl;
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attr.fifo_attr.txdl_term = vxge_tx_term;
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@ -2710,9 +2725,10 @@ vxge_open(struct net_device *dev)
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vxge_os_timer(vdev->vp_reset_timer,
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vxge_poll_vp_reset, vdev, (HZ/2));
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if (vdev->vp_lockup_timer.function == NULL)
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vxge_os_timer(vdev->vp_lockup_timer,
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vxge_poll_vp_lockup, vdev, (HZ/2));
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/* There is no need to check for RxD leak and RxD lookup on Titan1A */
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if (vdev->titan1 && vdev->vp_lockup_timer.function == NULL)
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vxge_os_timer(vdev->vp_lockup_timer, vxge_poll_vp_lockup, vdev,
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HZ / 2);
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set_bit(__VXGE_STATE_CARD_UP, &vdev->state);
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@ -2844,7 +2860,9 @@ static int do_vxge_close(struct net_device *dev, int do_io)
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smp_wmb();
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}
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del_timer_sync(&vdev->vp_lockup_timer);
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if (vdev->titan1)
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del_timer_sync(&vdev->vp_lockup_timer);
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del_timer_sync(&vdev->vp_reset_timer);
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@ -3262,6 +3280,19 @@ static const struct net_device_ops vxge_netdev_ops = {
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#endif
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};
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static int __devinit vxge_device_revision(struct vxgedev *vdev)
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{
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int ret;
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u8 revision;
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ret = pci_read_config_byte(vdev->pdev, PCI_REVISION_ID, &revision);
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if (ret)
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return -EIO;
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vdev->titan1 = (revision == VXGE_HW_TITAN1_PCI_REVISION);
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return 0;
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}
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static int __devinit vxge_device_register(struct __vxge_hw_device *hldev,
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struct vxge_config *config,
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int high_dma, int no_of_vpath,
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@ -3302,6 +3333,10 @@ static int __devinit vxge_device_register(struct __vxge_hw_device *hldev,
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vdev->rx_csum = 1; /* Enable Rx CSUM by default. */
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vdev->rx_hwts = 0;
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ret = vxge_device_revision(vdev);
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if (ret < 0)
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goto _out1;
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SET_NETDEV_DEV(ndev, &vdev->pdev->dev);
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ndev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX |
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@ -29,6 +29,9 @@
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#define PCI_DEVICE_ID_TITAN_WIN 0x5733
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#define PCI_DEVICE_ID_TITAN_UNI 0x5833
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#define VXGE_HW_TITAN1_PCI_REVISION 1
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#define VXGE_HW_TITAN1A_PCI_REVISION 2
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#define VXGE_USE_DEFAULT 0xffffffff
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#define VXGE_HW_VPATH_MSIX_ACTIVE 4
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#define VXGE_ALARM_MSIX_ID 2
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@ -53,11 +56,13 @@
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#define VXGE_TTI_BTIMER_VAL 250000
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#define VXGE_TTI_LTIMER_VAL 1000
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#define VXGE_TTI_RTIMER_VAL 0
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#define VXGE_RTI_BTIMER_VAL 250
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#define VXGE_RTI_LTIMER_VAL 100
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#define VXGE_RTI_RTIMER_VAL 0
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#define VXGE_TTI_LTIMER_VAL 1000
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#define VXGE_T1A_TTI_LTIMER_VAL 80
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#define VXGE_TTI_RTIMER_VAL 0
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#define VXGE_T1A_TTI_RTIMER_VAL 400
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#define VXGE_RTI_BTIMER_VAL 250
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#define VXGE_RTI_LTIMER_VAL 100
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#define VXGE_RTI_RTIMER_VAL 0
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#define VXGE_FIFO_INDICATE_MAX_PKTS VXGE_DEF_FIFO_LENGTH
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#define VXGE_ISR_POLLING_CNT 8
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#define VXGE_MAX_CONFIG_DEV 0xFF
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@ -76,14 +81,32 @@
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#define TTI_TX_UFC_B 40
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#define TTI_TX_UFC_C 60
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#define TTI_TX_UFC_D 100
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#define TTI_T1A_TX_UFC_A 30
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#define TTI_T1A_TX_UFC_B 80
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/* Slope - (max_mtu - min_mtu)/(max_mtu_ufc - min_mtu_ufc) */
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/* Slope - 93 */
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/* 60 - 9k Mtu, 140 - 1.5k mtu */
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#define TTI_T1A_TX_UFC_C(mtu) (60 + ((VXGE_HW_MAX_MTU - mtu) / 93))
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/* Slope - 37 */
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/* 100 - 9k Mtu, 300 - 1.5k mtu */
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#define TTI_T1A_TX_UFC_D(mtu) (100 + ((VXGE_HW_MAX_MTU - mtu) / 37))
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#define RTI_RX_URANGE_A 5
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#define RTI_RX_URANGE_B 15
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#define RTI_RX_URANGE_C 40
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#define RTI_T1A_RX_URANGE_A 1
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#define RTI_T1A_RX_URANGE_B 20
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#define RTI_T1A_RX_URANGE_C 50
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#define RTI_RX_UFC_A 1
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#define RTI_RX_UFC_B 5
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#define RTI_RX_UFC_C 10
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#define RTI_RX_UFC_D 15
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#define RTI_T1A_RX_UFC_B 20
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#define RTI_T1A_RX_UFC_C 50
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#define RTI_T1A_RX_UFC_D 60
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#define RTI_RX_URANGE_A 5
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#define RTI_RX_URANGE_B 15
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#define RTI_RX_URANGE_C 40
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#define RTI_RX_UFC_A 1
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#define RTI_RX_UFC_B 5
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#define RTI_RX_UFC_C 10
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#define RTI_RX_UFC_D 15
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/* Milli secs timer period */
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#define VXGE_TIMER_DELAY 10000
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@ -329,7 +352,8 @@ struct vxgedev {
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/* A flag indicating whether rx_csum is to be used or not. */
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u32 rx_csum:1,
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rx_hwts:1;
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rx_hwts:1,
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titan1:1;
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struct vxge_msix_entry *vxge_entries;
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struct msix_entry *entries;
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@ -397,6 +421,7 @@ struct vxge_tx_priv {
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} while (0);
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extern void vxge_initialize_ethtool_ops(struct net_device *ndev);
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enum vxge_hw_status vxge_reset_all_vpaths(struct vxgedev *vdev);
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int vxge_fw_upgrade(struct vxgedev *vdev, char *fw_name, int override);
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