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x86/fpu: Explain the AVX register layout in the xsave area

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The previous explanation was rather cryptic.

Also transform "u32 [64]" to the more readable "u8[256]" form.

No change in implementation.

Reviewed-by: Borislav Petkov <bp@alien8.de>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Fenghua Yu <fenghua.yu@intel.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Ingo Molnar 2015-04-24 11:43:47 +02:00
parent 678eaf6034
commit e783e8167d
1 changed files with 9 additions and 2 deletions
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11
arch/x86/include/asm/fpu/types.h
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@ -78,9 +78,16 @@ struct i387_soft_struct {
u32 entry_eip;
};
/*
* There are 16x 256-bit AVX registers named YMM0-YMM15.
* The low 128 bits are aliased to the 16 SSE registers (XMM0-XMM15)
* and are stored in 'struct i387_fxsave_struct::xmm_space[]'.
*
* The high 128 bits are stored here:
* 16x 128 bits == 256 bytes.
*/
struct ymmh_struct {
/* 16 * 16 bytes for each YMMH-reg = 256 bytes */
u32 ymmh_space[64];
u8 ymmh_space[256];
};
/* We don't support LWP yet: */