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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-24 12:30:53 +07:00
stmmac: use of_property_read_u32 instead of read_u8
Numbers in DT are stored in “cells” which are 32-bits in size. of_property_read_u8 does not work properly because of endianness problem. This causes it to always return 0 with little-endian architectures. Fix it by using of_property_read_u32() OF API. Signed-off-by: Bhadram Varka <vbhadram@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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2f2b1ae24c
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@ -168,8 +168,8 @@ static void stmmac_mtl_setup(struct platform_device *pdev,
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}
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/* Processing RX queues common config */
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if (of_property_read_u8(rx_node, "snps,rx-queues-to-use",
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&plat->rx_queues_to_use))
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if (of_property_read_u32(rx_node, "snps,rx-queues-to-use",
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&plat->rx_queues_to_use))
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plat->rx_queues_to_use = 1;
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if (of_property_read_bool(rx_node, "snps,rx-sched-sp"))
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@ -191,8 +191,8 @@ static void stmmac_mtl_setup(struct platform_device *pdev,
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else
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plat->rx_queues_cfg[queue].mode_to_use = MTL_QUEUE_DCB;
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if (of_property_read_u8(q_node, "snps,map-to-dma-channel",
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&plat->rx_queues_cfg[queue].chan))
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if (of_property_read_u32(q_node, "snps,map-to-dma-channel",
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&plat->rx_queues_cfg[queue].chan))
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plat->rx_queues_cfg[queue].chan = queue;
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/* TODO: Dynamic mapping to be included in the future */
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@ -222,8 +222,8 @@ static void stmmac_mtl_setup(struct platform_device *pdev,
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}
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/* Processing TX queues common config */
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if (of_property_read_u8(tx_node, "snps,tx-queues-to-use",
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&plat->tx_queues_to_use))
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if (of_property_read_u32(tx_node, "snps,tx-queues-to-use",
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&plat->tx_queues_to_use))
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plat->tx_queues_to_use = 1;
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if (of_property_read_bool(tx_node, "snps,tx-sched-wrr"))
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@ -244,8 +244,8 @@ static void stmmac_mtl_setup(struct platform_device *pdev,
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if (queue >= plat->tx_queues_to_use)
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break;
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if (of_property_read_u8(q_node, "snps,weight",
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&plat->tx_queues_cfg[queue].weight))
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if (of_property_read_u32(q_node, "snps,weight",
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&plat->tx_queues_cfg[queue].weight))
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plat->tx_queues_cfg[queue].weight = 0x10 + queue;
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if (of_property_read_bool(q_node, "snps,dcb-algorithm")) {
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@ -126,14 +126,14 @@ struct stmmac_axi {
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struct stmmac_rxq_cfg {
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u8 mode_to_use;
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u8 chan;
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u32 chan;
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u8 pkt_route;
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bool use_prio;
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u32 prio;
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};
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struct stmmac_txq_cfg {
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u8 weight;
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u32 weight;
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u8 mode_to_use;
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/* Credit Base Shaper parameters */
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u32 send_slope;
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@ -168,8 +168,8 @@ struct plat_stmmacenet_data {
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int unicast_filter_entries;
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int tx_fifo_size;
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int rx_fifo_size;
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u8 rx_queues_to_use;
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u8 tx_queues_to_use;
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u32 rx_queues_to_use;
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u32 tx_queues_to_use;
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u8 rx_sched_algorithm;
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u8 tx_sched_algorithm;
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struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
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