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Merge branch 'clockevents/4.13' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core

Browse Source 
Pull clockevent changes from Daniel Lezcano:

 - Factored out moxart, aspeed, cortina drivers into a generic timer fttrm010.
   Take the opportunity to add the delay timer (Linus Walleij)

 - Saved / restored tcb atmel context at suspend/resume (Alexandre Belloni)

 - Added ast2500 compatible string and fixed aspeed2500 initialization (Daniel
   Lezcano)

 - Added clock names property for aspeed (Andrew Jeffery)

 - Renamed clocksource_of to timer_of (Daniel Lezcano)

 - Added a common timer init routine (Daniel Lezcano)
This commit is contained in:
Thomas Gleixner 2017-06-20 12:35:36 +02:00
commit e707eb762c
111 changed files with 802 additions and 754 deletions
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6
Documentation/devicetree/bindings/timer/faraday,fttmr010.txt
View File

@ -7,7 +7,11 @@ Required properties:
- compatible : Must be one of
"faraday,fttmr010"
"cortina,gemini-timer"
"cortina,gemini-timer", "faraday,fttmr010"
"moxa,moxart-timer", "faraday,fttmr010"
"aspeed,ast2400-timer"
"aspeed,ast2500-timer"
- reg : Should contain registers location and length
- interrupts : Should contain the three timer interrupts usually with
flags for falling edge

19
Documentation/devicetree/bindings/timer/moxa,moxart-timer.txt
View File

@ -1,19 +0,0 @@
MOXA ART timer
Required properties:
- compatible : Must be one of:
- "moxa,moxart-timer"
- "aspeed,ast2400-timer"
- reg : Should contain registers location and length
- interrupts : Should contain the timer interrupt number
- clocks : Should contain phandle for the clock that drives the counter
Example:
timer: timer@98400000 {
compatible = "moxa,moxart-timer";
reg = <0x98400000 0x42>;
interrupts = <19 1>;
clocks = <&coreclk>;
};

2
arch/arc/kernel/setup.c
View File

@ -470,7 +470,7 @@ void __init setup_arch(char **cmdline_p)
void __init time_init(void)
{
of_clk_init(NULL);
clocksource_probe();
timer_probe();
}
static int __init customize_machine(void)

10
arch/arm/Kconfig
View File

@ -337,7 +337,7 @@ config ARCH_MULTIPLATFORM
select ARM_HAS_SG_CHAIN
select ARM_PATCH_PHYS_VIRT
select AUTO_ZRELADDR
select CLKSRC_OF
select TIMER_OF
select COMMON_CLK
select GENERIC_CLOCKEVENTS
select MIGHT_HAVE_PCI
@ -351,7 +351,7 @@ config ARM_SINGLE_ARMV7M
depends on !MMU
select ARM_NVIC
select AUTO_ZRELADDR
select CLKSRC_OF
select TIMER_OF
select COMMON_CLK
select CPU_V7M
select GENERIC_CLOCKEVENTS
@ -532,7 +532,7 @@ config ARCH_PXA
select CLKDEV_LOOKUP
select CLKSRC_PXA
select CLKSRC_MMIO
select CLKSRC_OF
select TIMER_OF
select CPU_XSCALE if !CPU_XSC3
select GENERIC_CLOCKEVENTS
select GPIO_PXA
@ -571,7 +571,7 @@ config ARCH_SA1100
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select CLKSRC_PXA
select CLKSRC_OF if OF
select TIMER_OF if OF
select CPU_FREQ
select CPU_SA1100
select GENERIC_CLOCKEVENTS
@ -1357,7 +1357,7 @@ config HAVE_ARM_ARCH_TIMER
config HAVE_ARM_TWD
bool
select CLKSRC_OF if OF
select TIMER_OF if OF
help
This options enables support for the ARM timer and watchdog unit

1
arch/arm/boot/dts/aspeed-g4.dtsi
View File

@ -893,6 +893,7 @@ timer: timer@1e782000 {
//interrupts = <16 17 18 35 36 37 38 39>;
interrupts = <16>;
clocks = <&clk_apb>;
clock-names = "PCLK";
};
wdt1: wdt@1e785000 {

1
arch/arm/boot/dts/aspeed-g5.dtsi
View File

@ -1000,6 +1000,7 @@ timer: timer@1e782000 {
//interrupts = <16 17 18 35 36 37 38 39>;
interrupts = <16>;
clocks = <&clk_apb>;
clock-names = "PCLK";
};

6
arch/arm/kernel/smp_twd.c
View File

@ -403,7 +403,7 @@ static int __init twd_local_timer_of_register(struct device_node *np)
WARN(err, "twd_local_timer_of_register failed (%d)\n", err);
return err;
}
CLOCKSOURCE_OF_DECLARE(arm_twd_a9, "arm,cortex-a9-twd-timer", twd_local_timer_of_register);
CLOCKSOURCE_OF_DECLARE(arm_twd_a5, "arm,cortex-a5-twd-timer", twd_local_timer_of_register);
CLOCKSOURCE_OF_DECLARE(arm_twd_11mp, "arm,arm11mp-twd-timer", twd_local_timer_of_register);
TIMER_OF_DECLARE(arm_twd_a9, "arm,cortex-a9-twd-timer", twd_local_timer_of_register);
TIMER_OF_DECLARE(arm_twd_a5, "arm,cortex-a5-twd-timer", twd_local_timer_of_register);
TIMER_OF_DECLARE(arm_twd_11mp, "arm,arm11mp-twd-timer", twd_local_timer_of_register);
#endif

2
arch/arm/kernel/time.c
View File

@ -120,6 +120,6 @@ void __init time_init(void)
#ifdef CONFIG_COMMON_CLK
of_clk_init(NULL);
#endif
clocksource_probe();
timer_probe();
}
}

2
arch/arm/mach-aspeed/Kconfig
View File

@ -4,7 +4,7 @@ menuconfig ARCH_ASPEED
select SRAM
select WATCHDOG
select ASPEED_WATCHDOG
select MOXART_TIMER
select FTTMR010_TIMER
select MFD_SYSCON
select PINCTRL
help

2
arch/arm/mach-bcm/Kconfig
View File

@ -150,7 +150,7 @@ config ARCH_BCM2835
select ARM_ERRATA_411920 if ARCH_MULTI_V6
select ARM_TIMER_SP804
select HAVE_ARM_ARCH_TIMER if ARCH_MULTI_V7
select CLKSRC_OF
select TIMER_OF
select BCM2835_TIMER
select PINCTRL
select PINCTRL_BCM2835

2
arch/arm/mach-clps711x/Kconfig
View File

@ -2,7 +2,7 @@ menuconfig ARCH_CLPS711X
bool "Cirrus Logic EP721x/EP731x-based"
depends on ARCH_MULTI_V4T
select AUTO_ZRELADDR
select CLKSRC_OF
select TIMER_OF
select CLPS711X_TIMER
select COMMON_CLK
select CPU_ARM720T

2
arch/arm/mach-mediatek/mediatek.c
View File

@ -41,7 +41,7 @@ static void __init mediatek_timer_init(void)
}
of_clk_init(NULL);
clocksource_probe();
timer_probe();
};
static const char * const mediatek_board_dt_compat[] = {

2
arch/arm/mach-moxart/Kconfig
View File

@ -4,7 +4,7 @@ menuconfig ARCH_MOXART
select CPU_FA526
select ARM_DMA_MEM_BUFFERABLE
select FARADAY_FTINTC010
select MOXART_TIMER
select FTTMR010_TIMER
select GPIOLIB
select PHYLIB if NETDEVICES
help

10
arch/arm/mach-omap2/timer.c
View File

@ -497,7 +497,7 @@ void __init omap_init_time(void)
__omap_sync32k_timer_init(1, "timer_32k_ck", "ti,timer-alwon",
2, "timer_sys_ck", NULL, false);
clocksource_probe();
timer_probe();
}
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_SOC_AM43XX)
@ -506,7 +506,7 @@ void __init omap3_secure_sync32k_timer_init(void)
__omap_sync32k_timer_init(12, "secure_32k_fck", "ti,timer-secure",
2, "timer_sys_ck", NULL, false);
clocksource_probe();
timer_probe();
}
#endif /* CONFIG_ARCH_OMAP3 */
@ -517,7 +517,7 @@ void __init omap3_gptimer_timer_init(void)
__omap_sync32k_timer_init(2, "timer_sys_ck", NULL,
1, "timer_sys_ck", "ti,timer-alwon", true);
if (of_have_populated_dt())
clocksource_probe();
timer_probe();
}
#endif
@ -532,7 +532,7 @@ static void __init omap4_sync32k_timer_init(void)
void __init omap4_local_timer_init(void)
{
omap4_sync32k_timer_init();
clocksource_probe();
timer_probe();
}
#endif
@ -656,7 +656,7 @@ void __init omap5_realtime_timer_init(void)
omap4_sync32k_timer_init();
realtime_counter_init();
clocksource_probe();
timer_probe();
}
#endif /* CONFIG_SOC_OMAP5 || CONFIG_SOC_DRA7XX */

2
arch/arm/mach-rockchip/rockchip.c
View File

@ -55,7 +55,7 @@ static void __init rockchip_timer_init(void)
}
of_clk_init(NULL);
clocksource_probe();
timer_probe();
}
static void __init rockchip_dt_init(void)

2
arch/arm/mach-s3c24xx/Kconfig
View File

@ -394,7 +394,7 @@ config MACH_SMDK2416
config MACH_S3C2416_DT
bool "Samsung S3C2416 machine using devicetree"
select CLKSRC_OF
select TIMER_OF
select USE_OF
select PINCTRL
select PINCTRL_S3C24XX

2
arch/arm/mach-s3c64xx/Kconfig
View File

@ -336,7 +336,7 @@ config MACH_WLF_CRAGG_6410
config MACH_S3C64XX_DT
bool "Samsung S3C6400/S3C6410 machine using Device Tree"
select CLKSRC_OF
select TIMER_OF
select CPU_S3C6400
select CPU_S3C6410
select PINCTRL

2
arch/arm/mach-shmobile/setup-rcar-gen2.c
View File

@ -113,7 +113,7 @@ void __init rcar_gen2_timer_init(void)
#endif /* CONFIG_ARM_ARCH_TIMER */
of_clk_init(NULL);
clocksource_probe();
timer_probe();
}
struct memory_reserve_config {

2
arch/arm/mach-spear/spear13xx.c
View File

@ -124,5 +124,5 @@ void __init spear13xx_timer_init(void)
clk_put(pclk);
spear_setup_of_timer();
clocksource_probe();
timer_probe();
}

2
arch/arm/mach-sunxi/sunxi.c
View File

@ -42,7 +42,7 @@ static void __init sun6i_timer_init(void)
of_clk_init(NULL);
if (IS_ENABLED(CONFIG_RESET_CONTROLLER))
sun6i_reset_init();
clocksource_probe();
timer_probe();
}
DT_MACHINE_START(SUN6I_DT, "Allwinner sun6i (A31) Family")

2
arch/arm/mach-u300/core.c
View File

@ -407,7 +407,7 @@ static const char * u300_board_compat[] = {
DT_MACHINE_START(U300_DT, "U300 S335/B335 (Device Tree)")
.map_io = u300_map_io,
.init_irq = u300_init_irq_dt,
.init_time = clocksource_probe,
.init_time = timer_probe,
.init_machine = u300_init_machine_dt,
.restart = u300_restart,
.dt_compat = u300_board_compat,

2
arch/arm/mach-zynq/common.c
View File

@ -150,7 +150,7 @@ static void __init zynq_timer_init(void)
{
zynq_clock_init();
of_clk_init(NULL);
clocksource_probe();
timer_probe();
}
static struct map_desc zynq_cortex_a9_scu_map __initdata = {

4
arch/arm64/Kconfig.platforms
View File

@ -18,7 +18,7 @@ config ARCH_ALPINE
config ARCH_BCM2835
bool "Broadcom BCM2835 family"
select CLKSRC_OF
select TIMER_OF
select GPIOLIB
select PINCTRL
select PINCTRL_BCM2835
@ -178,7 +178,7 @@ config ARCH_TEGRA
select ARCH_HAS_RESET_CONTROLLER
select CLKDEV_LOOKUP
select CLKSRC_MMIO
select CLKSRC_OF
select TIMER_OF
select GENERIC_CLOCKEVENTS
select GPIOLIB
select PINCTRL

2
arch/arm64/kernel/time.c
View File

@ -70,7 +70,7 @@ void __init time_init(void)
u32 arch_timer_rate;
of_clk_init(NULL);
clocksource_probe();
timer_probe();
tick_setup_hrtimer_broadcast();

2
arch/h8300/Kconfig
View File

@ -15,7 +15,7 @@ config H8300
select OF_IRQ
select OF_EARLY_FLATTREE
select HAVE_MEMBLOCK
select CLKSRC_OF
select TIMER_OF
select H8300_TMR8
select HAVE_KERNEL_GZIP
select HAVE_KERNEL_LZO

2
arch/h8300/kernel/setup.c
View File

@ -246,5 +246,5 @@ void __init calibrate_delay(void)
void __init time_init(void)
{
of_clk_init(NULL);
clocksource_probe();
timer_probe();
}

2
arch/microblaze/Kconfig
View File

@ -4,7 +4,7 @@ config MICROBLAZE
select ARCH_MIGHT_HAVE_PC_PARPORT
select ARCH_WANT_IPC_PARSE_VERSION
select BUILDTIME_EXTABLE_SORT
select CLKSRC_OF
select TIMER_OF
select CLONE_BACKWARDS3
select COMMON_CLK
select GENERIC_ATOMIC64

2
arch/microblaze/kernel/setup.c
View File

@ -192,7 +192,7 @@ void __init time_init(void)
{
of_clk_init(NULL);
setup_cpuinfo_clk();
clocksource_probe();
timer_probe();
}
#ifdef CONFIG_DEBUG_FS

2
arch/microblaze/kernel/timer.c
View File

@ -333,5 +333,5 @@ static int __init xilinx_timer_init(struct device_node *timer)
return 0;
}
CLOCKSOURCE_OF_DECLARE(xilinx_timer, "xlnx,xps-timer-1.00.a",
TIMER_OF_DECLARE(xilinx_timer, "xlnx,xps-timer-1.00.a",
xilinx_timer_init);

2
arch/mips/generic/init.c
View File

@ -161,7 +161,7 @@ void __init plat_time_init(void)
}
}
clocksource_probe();
timer_probe();
}
void __init arch_init_irq(void)

2
arch/mips/mti-malta/malta-time.c
View File

@ -265,7 +265,7 @@ void __init plat_time_init(void)
(freq%1000000)*100/1000000);
#ifdef CONFIG_CLKSRC_MIPS_GIC
update_gic_frequency_dt();
clocksource_probe();
timer_probe();
#endif
}
#endif

2
arch/mips/pic32/pic32mzda/time.c
View File

@ -64,5 +64,5 @@ void __init plat_time_init(void)
pr_info("CPU Clock: %ldMHz\n", rate / 1000000);
mips_hpt_frequency = rate / 2;
clocksource_probe();
timer_probe();
}

2
arch/mips/pistachio/time.c
View File

@ -39,7 +39,7 @@ void __init plat_time_init(void)
struct clk *clk;
of_clk_init(NULL);
clocksource_probe();
timer_probe();
np = of_get_cpu_node(0, NULL);
if (!np) {

2
arch/mips/ralink/Kconfig
View File

@ -4,7 +4,7 @@ config CLKEVT_RT3352
bool
depends on SOC_RT305X || SOC_MT7620
default y
select CLKSRC_OF
select TIMER_OF
select CLKSRC_MMIO
config RALINK_ILL_ACC

2
arch/mips/ralink/cevt-rt3352.c
View File

@ -152,4 +152,4 @@ static int __init ralink_systick_init(struct device_node *np)
return 0;
}
CLOCKSOURCE_OF_DECLARE(systick, "ralink,cevt-systick", ralink_systick_init);
TIMER_OF_DECLARE(systick, "ralink,cevt-systick", ralink_systick_init);

2
arch/mips/ralink/clk.c
View File

@ -82,5 +82,5 @@ void __init plat_time_init(void)
pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
mips_hpt_frequency = clk_get_rate(clk) / 2;
clk_put(clk);
clocksource_probe();
timer_probe();
}

2
arch/mips/ralink/timer-gic.c
View File

@ -20,5 +20,5 @@ void __init plat_time_init(void)
ralink_of_remap();
of_clk_init(NULL);
clocksource_probe();
timer_probe();
}

2
arch/mips/xilfpga/time.c
View File

@ -22,7 +22,7 @@ void __init plat_time_init(void)
struct clk *clk;
of_clk_init(NULL);
clocksource_probe();
timer_probe();
np = of_get_cpu_node(0, NULL);
if (!np) {

2
arch/nios2/Kconfig
View File

@ -1,6 +1,6 @@
config NIOS2
def_bool y
select CLKSRC_OF
select TIMER_OF
select GENERIC_ATOMIC64
select GENERIC_CLOCKEVENTS
select GENERIC_CPU_DEVICES

4
arch/nios2/kernel/time.c
View File

@ -350,7 +350,7 @@ void __init time_init(void)
if (count < 2)
panic("%d timer is found, it needs 2 timers in system\n", count);
clocksource_probe();
timer_probe();
}
CLOCKSOURCE_OF_DECLARE(nios2_timer, ALTR_TIMER_COMPATIBLE, nios2_time_init);
TIMER_OF_DECLARE(nios2_timer, ALTR_TIMER_COMPATIBLE, nios2_time_init);

2
arch/sh/boards/Kconfig
View File

@ -10,7 +10,7 @@ config SH_DEVICE_TREE
bool "Board Described by Device Tree"
select OF
select OF_EARLY_FLATTREE
select CLKSRC_OF
select TIMER_OF
select COMMON_CLK
select GENERIC_CALIBRATE_DELAY
help

2
arch/sh/boards/of-generic.c
View File

@ -119,7 +119,7 @@ static void __init sh_of_mem_reserve(void)
static void __init sh_of_time_init(void)
{
pr_info("SH generic board support: scanning for clocksource devices\n");
clocksource_probe();
timer_probe();
}
static void __init sh_of_setup(char **cmdline_p)

2
arch/xtensa/kernel/time.c
View File

@ -187,7 +187,7 @@ void __init time_init(void)
local_timer_setup(0);
setup_irq(this_cpu_ptr(&ccount_timer)->evt.irq, &timer_irqaction);
sched_clock_register(ccount_sched_clock_read, 32, ccount_freq);
clocksource_probe();
timer_probe();
}
/*

79
drivers/clocksource/Kconfig
View File

@ -1,22 +1,16 @@
menu "Clock Source drivers"
depends on !ARCH_USES_GETTIMEOFFSET
config CLKSRC_OF
config TIMER_OF
bool
select CLKSRC_PROBE
depends on GENERIC_CLOCKEVENTS
select TIMER_PROBE
config CLKEVT_OF
config TIMER_ACPI
bool
select CLKEVT_PROBE
select TIMER_PROBE
config CLKSRC_ACPI
bool
select CLKSRC_PROBE
config CLKSRC_PROBE
bool
config CLKEVT_PROBE
config TIMER_PROBE
bool
config CLKSRC_I8253
@ -65,14 +59,14 @@ config DW_APB_TIMER
config DW_APB_TIMER_OF
bool
select DW_APB_TIMER
select CLKSRC_OF
select TIMER_OF
config FTTMR010_TIMER
bool "Faraday Technology timer driver" if COMPILE_TEST
depends on GENERIC_CLOCKEVENTS
depends on HAS_IOMEM
select CLKSRC_MMIO
select CLKSRC_OF
select TIMER_OF
select MFD_SYSCON
help
Enables support for the Faraday Technology timer block
@ -81,7 +75,7 @@ config FTTMR010_TIMER
config ROCKCHIP_TIMER
bool "Rockchip timer driver" if COMPILE_TEST
depends on ARM || ARM64
select CLKSRC_OF
select TIMER_OF
select CLKSRC_MMIO
help
Enables the support for the rockchip timer driver.
@ -89,7 +83,7 @@ config ROCKCHIP_TIMER
config ARMADA_370_XP_TIMER
bool "Armada 370 and XP timer driver" if COMPILE_TEST
depends on ARM
select CLKSRC_OF
select TIMER_OF
select CLKSRC_MMIO
help
Enables the support for the Armada 370 and XP timer driver.
@ -104,7 +98,7 @@ config MESON6_TIMER
config ORION_TIMER
bool "Orion timer driver" if COMPILE_TEST
depends on ARM
select CLKSRC_OF
select TIMER_OF
select CLKSRC_MMIO
help
Enables the support for the Orion timer driver
@ -148,7 +142,7 @@ config ASM9260_TIMER
bool "ASM9260 timer driver" if COMPILE_TEST
depends on GENERIC_CLOCKEVENTS
select CLKSRC_MMIO
select CLKSRC_OF
select TIMER_OF
help
Enables support for the ASM9260 timer.
@ -188,13 +182,6 @@ config ATLAS7_TIMER
help
Enables support for the Atlas7 timer.
config MOXART_TIMER
bool "Moxart timer driver" if COMPILE_TEST
depends on GENERIC_CLOCKEVENTS
select CLKSRC_MMIO
help
Enables support for the Moxart timer.
config MXS_TIMER
bool "Mxs timer driver" if COMPILE_TEST
depends on GENERIC_CLOCKEVENTS
@ -261,21 +248,21 @@ config CLKSRC_LPC32XX
depends on GENERIC_CLOCKEVENTS && HAS_IOMEM
depends on ARM
select CLKSRC_MMIO
select CLKSRC_OF
select TIMER_OF
help
Support for the LPC32XX clocksource.
config CLKSRC_PISTACHIO
bool "Clocksource for Pistachio SoC" if COMPILE_TEST
depends on HAS_IOMEM
select CLKSRC_OF
select TIMER_OF
help
Enables the clocksource for the Pistachio SoC.
config CLKSRC_TI_32K
bool "Texas Instruments 32.768 Hz Clocksource" if COMPILE_TEST
depends on GENERIC_SCHED_CLOCK
select CLKSRC_OF if OF
select TIMER_OF if OF
help
This option enables support for Texas Instruments 32.768 Hz clocksource
available on many OMAP-like platforms.
@ -284,7 +271,7 @@ config CLKSRC_NPS
bool "NPS400 clocksource driver" if COMPILE_TEST
depends on !PHYS_ADDR_T_64BIT
select CLKSRC_MMIO
select CLKSRC_OF if OF
select TIMER_OF if OF
help
NPS400 clocksource support.
Got 64 bit counter with update rate up to 1000MHz.
@ -299,12 +286,12 @@ config CLKSRC_MPS2
bool "Clocksource for MPS2 SoCs" if COMPILE_TEST
depends on GENERIC_SCHED_CLOCK
select CLKSRC_MMIO
select CLKSRC_OF
select TIMER_OF
config ARC_TIMERS
bool "Support for 32-bit TIMERn counters in ARC Cores" if COMPILE_TEST
depends on GENERIC_CLOCKEVENTS
select CLKSRC_OF
select TIMER_OF
help
These are legacy 32-bit TIMER0 and TIMER1 counters found on all ARC cores
(ARC700 as well as ARC HS38).
@ -314,7 +301,7 @@ config ARC_TIMERS_64BIT
bool "Support for 64-bit counters in ARC HS38 cores" if COMPILE_TEST
depends on GENERIC_CLOCKEVENTS
depends on ARC_TIMERS
select CLKSRC_OF
select TIMER_OF
help
This enables 2 different 64-bit timers: RTC (for UP) and GFRC (for SMP)
RTC is implemented inside the core, while GFRC sits outside the core in
@ -323,8 +310,8 @@ config ARC_TIMERS_64BIT
config ARM_ARCH_TIMER
bool
select CLKSRC_OF if OF
select CLKSRC_ACPI if ACPI
select TIMER_OF if OF
select TIMER_ACPI if ACPI
config ARM_ARCH_TIMER_EVTSTREAM
bool "Enable ARM architected timer event stream generation by default"
@ -381,7 +368,7 @@ config ARM64_ERRATUM_858921
config ARM_GLOBAL_TIMER
bool "Support for the ARM global timer" if COMPILE_TEST
select CLKSRC_OF if OF
select TIMER_OF if OF
depends on ARM
help
This options enables support for the ARM global timer unit
@ -390,7 +377,7 @@ config ARM_TIMER_SP804
bool "Support for Dual Timer SP804 module"
depends on GENERIC_SCHED_CLOCK && CLKDEV_LOOKUP
select CLKSRC_MMIO
select CLKSRC_OF if OF
select TIMER_OF if OF
config CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
bool
@ -401,19 +388,19 @@ config CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
config ARMV7M_SYSTICK
bool "Support for the ARMv7M system time" if COMPILE_TEST
select CLKSRC_OF if OF
select TIMER_OF if OF
select CLKSRC_MMIO
help
This options enables support for the ARMv7M system timer unit
config ATMEL_PIT
select CLKSRC_OF if OF
select TIMER_OF if OF
def_bool SOC_AT91SAM9 || SOC_SAMA5
config ATMEL_ST
bool "Atmel ST timer support" if COMPILE_TEST
depends on GENERIC_CLOCKEVENTS
select CLKSRC_OF
select TIMER_OF
select MFD_SYSCON
help
Support for the Atmel ST timer.
@ -456,7 +443,7 @@ config VF_PIT_TIMER
config OXNAS_RPS_TIMER
bool "Oxford Semiconductor OXNAS RPS Timers driver" if COMPILE_TEST
depends on GENERIC_CLOCKEVENTS
select CLKSRC_OF
select TIMER_OF
select CLKSRC_MMIO
help
This enables support for the Oxford Semiconductor OXNAS RPS timers.
@ -467,7 +454,7 @@ config SYS_SUPPORTS_SH_CMT
config MTK_TIMER
bool "Mediatek timer driver" if COMPILE_TEST
depends on GENERIC_CLOCKEVENTS && HAS_IOMEM
select CLKSRC_OF
select TIMER_OF
select CLKSRC_MMIO
help
Support for Mediatek timer driver.
@ -540,7 +527,7 @@ config EM_TIMER_STI
config CLKSRC_QCOM
bool "Qualcomm MSM timer" if COMPILE_TEST
depends on ARM
select CLKSRC_OF
select TIMER_OF
help
This enables the clocksource and the per CPU clockevent driver for the
Qualcomm SoCs.
@ -548,7 +535,7 @@ config CLKSRC_QCOM
config CLKSRC_VERSATILE
bool "ARM Versatile (Express) reference platforms clock source" if COMPILE_TEST
depends on GENERIC_SCHED_CLOCK && !ARCH_USES_GETTIMEOFFSET
select CLKSRC_OF
select TIMER_OF
default y if MFD_VEXPRESS_SYSREG
help
This option enables clock source based on free running
@ -559,12 +546,12 @@ config CLKSRC_VERSATILE
config CLKSRC_MIPS_GIC
bool
depends on MIPS_GIC
select CLKSRC_OF
select TIMER_OF
config CLKSRC_TANGO_XTAL
bool "Clocksource for Tango SoC" if COMPILE_TEST
depends on ARM
select CLKSRC_OF
select TIMER_OF
select CLKSRC_MMIO
help
This enables the clocksource for Tango SoC
@ -605,7 +592,7 @@ config CLKSRC_IMX_GPT
config CLKSRC_ST_LPC
bool "Low power clocksource found in the LPC" if COMPILE_TEST
select CLKSRC_OF if OF
select TIMER_OF if OF
depends on HAS_IOMEM
select CLKSRC_MMIO
help

5
drivers/clocksource/Makefile
View File

@ -1,5 +1,5 @@
obj-$(CONFIG_CLKSRC_PROBE) += clksrc-probe.o
obj-$(CONFIG_CLKEVT_PROBE) += clkevt-probe.o
obj-$(CONFIG_TIMER_OF) += timer-of.o
obj-$(CONFIG_TIMER_PROBE) += timer-probe.o
obj-$(CONFIG_ATMEL_PIT) += timer-atmel-pit.o
obj-$(CONFIG_ATMEL_ST) += timer-atmel-st.o
obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o
@ -26,7 +26,6 @@ obj-$(CONFIG_ORION_TIMER) += time-orion.o
obj-$(CONFIG_BCM2835_TIMER) += bcm2835_timer.o
obj-$(CONFIG_CLPS711X_TIMER) += clps711x-timer.o
obj-$(CONFIG_ATLAS7_TIMER) += timer-atlas7.o
obj-$(CONFIG_MOXART_TIMER) += moxart_timer.o
obj-$(CONFIG_MXS_TIMER) += mxs_timer.o
obj-$(CONFIG_CLKSRC_PXA) += pxa_timer.o
obj-$(CONFIG_PRIMA2_TIMER) += timer-prima2.o

6
drivers/clocksource/arc_timer.c
View File

@ -99,7 +99,7 @@ static int __init arc_cs_setup_gfrc(struct device_node *node)
return clocksource_register_hz(&arc_counter_gfrc, arc_timer_freq);
}
CLOCKSOURCE_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc);
TIMER_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc);
#define AUX_RTC_CTRL 0x103
#define AUX_RTC_LOW 0x104
@ -158,7 +158,7 @@ static int __init arc_cs_setup_rtc(struct device_node *node)
return clocksource_register_hz(&arc_counter_rtc, arc_timer_freq);
}
CLOCKSOURCE_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc);
TIMER_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc);
#endif
@ -333,4 +333,4 @@ static int __init arc_of_timer_init(struct device_node *np)
return ret;
}
CLOCKSOURCE_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_of_timer_init);
TIMER_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_of_timer_init);

8
drivers/clocksource/arm_arch_timer.c
View File

@ -1194,8 +1194,8 @@ static int __init arch_timer_of_init(struct device_node *np)
return arch_timer_common_init();
}
CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init);
CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init);
TIMER_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init);
TIMER_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init);
static u32 __init
arch_timer_mem_frame_get_cntfrq(struct arch_timer_mem_frame *frame)
@ -1382,7 +1382,7 @@ static int __init arch_timer_mem_of_init(struct device_node *np)
kfree(timer_mem);
return ret;
}
CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
TIMER_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
arch_timer_mem_of_init);
#ifdef CONFIG_ACPI_GTDT
@ -1516,5 +1516,5 @@ static int __init arch_timer_acpi_init(struct acpi_table_header *table)
return arch_timer_common_init();
}
CLOCKSOURCE_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init);
TIMER_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init);
#endif

2
drivers/clocksource/arm_global_timer.c
View File

@ -339,5 +339,5 @@ static int __init global_timer_of_register(struct device_node *np)
}
/* Only tested on r2p2 and r3p0 */
CLOCKSOURCE_OF_DECLARE(arm_gt, "arm,cortex-a9-global-timer",
TIMER_OF_DECLARE(arm_gt, "arm,cortex-a9-global-timer",
global_timer_of_register);

2
drivers/clocksource/armv7m_systick.c
View File

@ -82,5 +82,5 @@ static int __init system_timer_of_register(struct device_node *np)
return ret;
}
CLOCKSOURCE_OF_DECLARE(arm_systick, "arm,armv7m-systick",
TIMER_OF_DECLARE(arm_systick, "arm,armv7m-systick",
system_timer_of_register);

2
drivers/clocksource/asm9260_timer.c
View File

@ -238,5 +238,5 @@ static int __init asm9260_timer_init(struct device_node *np)
return 0;
}
CLOCKSOURCE_OF_DECLARE(asm9260_timer, "alphascale,asm9260-timer",
TIMER_OF_DECLARE(asm9260_timer, "alphascale,asm9260-timer",
asm9260_timer_init);

2
drivers/clocksource/bcm2835_timer.c
View File

@ -148,5 +148,5 @@ static int __init bcm2835_timer_init(struct device_node *node)
iounmap(base);
return ret;
}
CLOCKSOURCE_OF_DECLARE(bcm2835, "brcm,bcm2835-system-timer",
TIMER_OF_DECLARE(bcm2835, "brcm,bcm2835-system-timer",
bcm2835_timer_init);

4
drivers/clocksource/bcm_kona_timer.c
View File

@ -198,9 +198,9 @@ static int __init kona_timer_init(struct device_node *node)
return 0;
}
CLOCKSOURCE_OF_DECLARE(brcm_kona, "brcm,kona-timer", kona_timer_init);
TIMER_OF_DECLARE(brcm_kona, "brcm,kona-timer", kona_timer_init);
/*
* bcm,kona-timer is deprecated by brcm,kona-timer
* being kept here for driver compatibility
*/
CLOCKSOURCE_OF_DECLARE(bcm_kona, "bcm,kona-timer", kona_timer_init);
TIMER_OF_DECLARE(bcm_kona, "bcm,kona-timer", kona_timer_init);

2
drivers/clocksource/cadence_ttc_timer.c
View File

@ -539,4 +539,4 @@ static int __init ttc_timer_init(struct device_node *timer)
return 0;
}
CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init);
TIMER_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init);

56
drivers/clocksource/clkevt-probe.c
View File

@ -1,56 +0,0 @@
/*
* Copyright (c) 2016, Linaro Ltd. All rights reserved.
* Daniel Lezcano <daniel.lezcano@linaro.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/init.h>
#include <linux/of.h>
#include <linux/clockchips.h>
extern struct of_device_id __clkevt_of_table[];
static const struct of_device_id __clkevt_of_table_sentinel
__used __section(__clkevt_of_table_end);
int __init clockevent_probe(void)
{
struct device_node *np;
const struct of_device_id *match;
of_init_fn_1_ret init_func;
int ret, clockevents = 0;
for_each_matching_node_and_match(np, __clkevt_of_table, &match) {
if (!of_device_is_available(np))
continue;
init_func = match->data;
ret = init_func(np);
if (ret) {
pr_warn("Failed to initialize '%s' (%d)\n",
np->name, ret);
continue;
}
clockevents++;
}
if (!clockevents) {
pr_crit("%s: no matching clockevent found\n", __func__);
return -ENODEV;
}
return 0;
}

2
drivers/clocksource/clksrc-dbx500-prcmu.c
View File

@ -86,5 +86,5 @@ static int __init clksrc_dbx500_prcmu_init(struct device_node *node)
#endif
return clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K);
}
CLOCKSOURCE_OF_DECLARE(dbx500_prcmu, "stericsson,db8500-prcmu-timer-4",
TIMER_OF_DECLARE(dbx500_prcmu, "stericsson,db8500-prcmu-timer-4",
clksrc_dbx500_prcmu_init);

2
drivers/clocksource/clksrc_st_lpc.c
View File

@ -132,4 +132,4 @@ static int __init st_clksrc_of_register(struct device_node *np)
return ret;
}
CLOCKSOURCE_OF_DECLARE(ddata, "st,stih407-lpc", st_clksrc_of_register);
TIMER_OF_DECLARE(ddata, "st,stih407-lpc", st_clksrc_of_register);

4
drivers/clocksource/clps711x-timer.c
View File

@ -103,7 +103,7 @@ void __init clps711x_clksrc_init(void __iomem *tc1_base, void __iomem *tc2_base,
BUG_ON(_clps711x_clkevt_init(tc2, tc2_base, irq));
}
#ifdef CONFIG_CLKSRC_OF
#ifdef CONFIG_TIMER_OF
static int __init clps711x_timer_init(struct device_node *np)
{
unsigned int irq = irq_of_parse_and_map(np, 0);
@ -119,5 +119,5 @@ static int __init clps711x_timer_init(struct device_node *np)
return -EINVAL;
}
}
CLOCKSOURCE_OF_DECLARE(clps711x, "cirrus,ep7209-timer", clps711x_timer_init);
TIMER_OF_DECLARE(clps711x, "cirrus,ep7209-timer", clps711x_timer_init);
#endif

8
drivers/clocksource/dw_apb_timer_of.c
View File

@ -167,7 +167,7 @@ static int __init dw_apb_timer_init(struct device_node *timer)
return 0;
}
CLOCKSOURCE_OF_DECLARE(pc3x2_timer, "picochip,pc3x2-timer", dw_apb_timer_init);
CLOCKSOURCE_OF_DECLARE(apb_timer_osc, "snps,dw-apb-timer-osc", dw_apb_timer_init);
CLOCKSOURCE_OF_DECLARE(apb_timer_sp, "snps,dw-apb-timer-sp", dw_apb_timer_init);
CLOCKSOURCE_OF_DECLARE(apb_timer, "snps,dw-apb-timer", dw_apb_timer_init);
TIMER_OF_DECLARE(pc3x2_timer, "picochip,pc3x2-timer", dw_apb_timer_init);
TIMER_OF_DECLARE(apb_timer_osc, "snps,dw-apb-timer-osc", dw_apb_timer_init);
TIMER_OF_DECLARE(apb_timer_sp, "snps,dw-apb-timer-sp", dw_apb_timer_init);
TIMER_OF_DECLARE(apb_timer, "snps,dw-apb-timer", dw_apb_timer_init);

4
drivers/clocksource/exynos_mct.c
View File

@ -610,5 +610,5 @@ static int __init mct_init_ppi(struct device_node *np)
{
return mct_init_dt(np, MCT_INT_PPI);
}
CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);
TIMER_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
TIMER_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);

2
drivers/clocksource/fsl_ftm_timer.c
View File

@ -369,4 +369,4 @@ static int __init ftm_timer_init(struct device_node *np)
kfree(priv);
return ret;
}
CLOCKSOURCE_OF_DECLARE(flextimer, "fsl,ftm-timer", ftm_timer_init);
TIMER_OF_DECLARE(flextimer, "fsl,ftm-timer", ftm_timer_init);

2
drivers/clocksource/h8300_timer16.c
View File

@ -187,5 +187,5 @@ static int __init h8300_16timer_init(struct device_node *node)
return ret;
}
CLOCKSOURCE_OF_DECLARE(h8300_16bit, "renesas,16bit-timer",
TIMER_OF_DECLARE(h8300_16bit, "renesas,16bit-timer",
h8300_16timer_init);

2
drivers/clocksource/h8300_timer8.c
View File

@ -207,4 +207,4 @@ static int __init h8300_8timer_init(struct device_node *node)
return ret;
}
CLOCKSOURCE_OF_DECLARE(h8300_8bit, "renesas,8bit-timer", h8300_8timer_init);
TIMER_OF_DECLARE(h8300_8bit, "renesas,8bit-timer", h8300_8timer_init);

2
drivers/clocksource/h8300_tpu.c
View File

@ -154,4 +154,4 @@ static int __init h8300_tpu_init(struct device_node *node)
return ret;
}
CLOCKSOURCE_OF_DECLARE(h8300_tpu, "renesas,tpu", h8300_tpu_init);
TIMER_OF_DECLARE(h8300_tpu, "renesas,tpu", h8300_tpu_init);

2
drivers/clocksource/jcore-pit.c
View File

@ -246,4 +246,4 @@ static int __init jcore_pit_init(struct device_node *node)
return 0;
}
CLOCKSOURCE_OF_DECLARE(jcore_pit, "jcore,pit", jcore_pit_init);
TIMER_OF_DECLARE(jcore_pit, "jcore,pit", jcore_pit_init);

2
drivers/clocksource/meson6_timer.c
View File

@ -174,5 +174,5 @@ static int __init meson6_timer_init(struct device_node *node)
1, 0xfffe);
return 0;
}
CLOCKSOURCE_OF_DECLARE(meson6, "amlogic,meson6-timer",
TIMER_OF_DECLARE(meson6, "amlogic,meson6-timer",
meson6_timer_init);

2
drivers/clocksource/mips-gic-timer.c
View File

@ -200,5 +200,5 @@ static int __init gic_clocksource_of_init(struct device_node *node)
return 0;
}
CLOCKSOURCE_OF_DECLARE(mips_gic_timer, "mti,gic-timer",
TIMER_OF_DECLARE(mips_gic_timer, "mti,gic-timer",
gic_clocksource_of_init);

256
drivers/clocksource/moxart_timer.c
View File

@ -1,256 +0,0 @@
/*
* MOXA ART SoCs timer handling.
*
* Copyright (C) 2013 Jonas Jensen
*
* Jonas Jensen <jonas.jensen@gmail.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/clk.h>
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqreturn.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/io.h>
#include <linux/clocksource.h>
#include <linux/bitops.h>
#include <linux/slab.h>
#define TIMER1_BASE 0x00
#define TIMER2_BASE 0x10
#define TIMER3_BASE 0x20
#define REG_COUNT 0x0 /* writable */
#define REG_LOAD 0x4
#define REG_MATCH1 0x8
#define REG_MATCH2 0xC
#define TIMER_CR 0x30
#define TIMER_INTR_STATE 0x34
#define TIMER_INTR_MASK 0x38
/*
* Moxart TIMER_CR flags:
*
* MOXART_CR_*_CLOCK 0: PCLK, 1: EXT1CLK
* MOXART_CR_*_INT overflow interrupt enable bit
*/
#define MOXART_CR_1_ENABLE BIT(0)
#define MOXART_CR_1_CLOCK BIT(1)
#define MOXART_CR_1_INT BIT(2)
#define MOXART_CR_2_ENABLE BIT(3)
#define MOXART_CR_2_CLOCK BIT(4)
#define MOXART_CR_2_INT BIT(5)
#define MOXART_CR_3_ENABLE BIT(6)
#define MOXART_CR_3_CLOCK BIT(7)
#define MOXART_CR_3_INT BIT(8)
#define MOXART_CR_COUNT_UP BIT(9)
#define MOXART_TIMER1_ENABLE (MOXART_CR_2_ENABLE | MOXART_CR_1_ENABLE)
#define MOXART_TIMER1_DISABLE (MOXART_CR_2_ENABLE)
/*
* The ASpeed variant of the IP block has a different layout
* for the control register
*/
#define ASPEED_CR_1_ENABLE BIT(0)
#define ASPEED_CR_1_CLOCK BIT(1)
#define ASPEED_CR_1_INT BIT(2)
#define ASPEED_CR_2_ENABLE BIT(4)
#define ASPEED_CR_2_CLOCK BIT(5)
#define ASPEED_CR_2_INT BIT(6)
#define ASPEED_CR_3_ENABLE BIT(8)
#define ASPEED_CR_3_CLOCK BIT(9)
#define ASPEED_CR_3_INT BIT(10)
#define ASPEED_TIMER1_ENABLE (ASPEED_CR_2_ENABLE | ASPEED_CR_1_ENABLE)
#define ASPEED_TIMER1_DISABLE (ASPEED_CR_2_ENABLE)
struct moxart_timer {
void __iomem *base;
unsigned int t1_disable_val;
unsigned int t1_enable_val;
unsigned int count_per_tick;
struct clock_event_device clkevt;
};
static inline struct moxart_timer *to_moxart(struct clock_event_device *evt)
{
return container_of(evt, struct moxart_timer, clkevt);
}
static inline void moxart_disable(struct clock_event_device *evt)
{
struct moxart_timer *timer = to_moxart(evt);
writel(timer->t1_disable_val, timer->base + TIMER_CR);
}
static inline void moxart_enable(struct clock_event_device *evt)
{
struct moxart_timer *timer = to_moxart(evt);
writel(timer->t1_enable_val, timer->base + TIMER_CR);
}
static int moxart_shutdown(struct clock_event_device *evt)
{
moxart_disable(evt);
return 0;
}
static int moxart_set_oneshot(struct clock_event_device *evt)
{
moxart_disable(evt);
writel(~0, to_moxart(evt)->base + TIMER1_BASE + REG_LOAD);
return 0;
}
static int moxart_set_periodic(struct clock_event_device *evt)
{
struct moxart_timer *timer = to_moxart(evt);
moxart_disable(evt);
writel(timer->count_per_tick, timer->base + TIMER1_BASE + REG_LOAD);
writel(0, timer->base + TIMER1_BASE + REG_MATCH1);
moxart_enable(evt);
return 0;
}
static int moxart_clkevt_next_event(unsigned long cycles,
struct clock_event_device *evt)
{
struct moxart_timer *timer = to_moxart(evt);
u32 u;
moxart_disable(evt);
u = readl(timer->base + TIMER1_BASE + REG_COUNT) - cycles;
writel(u, timer->base + TIMER1_BASE + REG_MATCH1);
moxart_enable(evt);
return 0;
}
static irqreturn_t moxart_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = dev_id;
evt->event_handler(evt);
return IRQ_HANDLED;
}
static int __init moxart_timer_init(struct device_node *node)
{
int ret, irq;
unsigned long pclk;
struct clk *clk;
struct moxart_timer *timer;
timer = kzalloc(sizeof(*timer), GFP_KERNEL);
if (!timer)
return -ENOMEM;
timer->base = of_iomap(node, 0);
if (!timer->base) {
pr_err("%s: of_iomap failed\n", node->full_name);
ret = -ENXIO;
goto out_free;
}
irq = irq_of_parse_and_map(node, 0);
if (irq <= 0) {
pr_err("%s: irq_of_parse_and_map failed\n", node->full_name);
ret = -EINVAL;
goto out_unmap;
}
clk = of_clk_get(node, 0);
if (IS_ERR(clk)) {
pr_err("%s: of_clk_get failed\n", node->full_name);
ret = PTR_ERR(clk);
goto out_unmap;
}
pclk = clk_get_rate(clk);
if (of_device_is_compatible(node, "moxa,moxart-timer")) {
timer->t1_enable_val = MOXART_TIMER1_ENABLE;
timer->t1_disable_val = MOXART_TIMER1_DISABLE;
} else if (of_device_is_compatible(node, "aspeed,ast2400-timer")) {
timer->t1_enable_val = ASPEED_TIMER1_ENABLE;
timer->t1_disable_val = ASPEED_TIMER1_DISABLE;
} else {
pr_err("%s: unknown platform\n", node->full_name);
ret = -EINVAL;
goto out_unmap;
}
timer->count_per_tick = DIV_ROUND_CLOSEST(pclk, HZ);
timer->clkevt.name = node->name;
timer->clkevt.rating = 200;
timer->clkevt.features = CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_ONESHOT;
timer->clkevt.set_state_shutdown = moxart_shutdown;
timer->clkevt.set_state_periodic = moxart_set_periodic;
timer->clkevt.set_state_oneshot = moxart_set_oneshot;
timer->clkevt.tick_resume = moxart_set_oneshot;
timer->clkevt.set_next_event = moxart_clkevt_next_event;
timer->clkevt.cpumask = cpumask_of(0);
timer->clkevt.irq = irq;
ret = clocksource_mmio_init(timer->base + TIMER2_BASE + REG_COUNT,
"moxart_timer", pclk, 200, 32,
clocksource_mmio_readl_down);
if (ret) {
pr_err("%s: clocksource_mmio_init failed\n", node->full_name);
goto out_unmap;
}
ret = request_irq(irq, moxart_timer_interrupt, IRQF_TIMER,
node->name, &timer->clkevt);
if (ret) {
pr_err("%s: setup_irq failed\n", node->full_name);
goto out_unmap;
}
/* Clear match registers */
writel(0, timer->base + TIMER1_BASE + REG_MATCH1);
writel(0, timer->base + TIMER1_BASE + REG_MATCH2);
writel(0, timer->base + TIMER2_BASE + REG_MATCH1);
writel(0, timer->base + TIMER2_BASE + REG_MATCH2);
/*
* Start timer 2 rolling as our main wall clock source, keep timer 1
* disabled
*/
writel(0, timer->base + TIMER_CR);
writel(~0, timer->base + TIMER2_BASE + REG_LOAD);
writel(timer->t1_disable_val, timer->base + TIMER_CR);
/*
* documentation is not publicly available:
* min_delta / max_delta obtained by trial-and-error,
* max_delta 0xfffffffe should be ok because count
* register size is u32
*/
clockevents_config_and_register(&timer->clkevt, pclk, 0x4, 0xfffffffe);
return 0;
out_unmap:
iounmap(timer->base);
out_free:
kfree(timer);
return ret;
}
CLOCKSOURCE_OF_DECLARE(moxart, "moxa,moxart-timer", moxart_timer_init);
CLOCKSOURCE_OF_DECLARE(aspeed, "aspeed,ast2400-timer", moxart_timer_init);

2
drivers/clocksource/mps2-timer.c
View File

@ -274,4 +274,4 @@ static int __init mps2_timer_init(struct device_node *np)
return 0;
}
CLOCKSOURCE_OF_DECLARE(mps2_timer, "arm,mps2-timer", mps2_timer_init);
TIMER_OF_DECLARE(mps2_timer, "arm,mps2-timer", mps2_timer_init);

2
drivers/clocksource/mtk_timer.c
View File

@ -265,4 +265,4 @@ static int __init mtk_timer_init(struct device_node *node)
return -EINVAL;
}
CLOCKSOURCE_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_timer_init);
TIMER_OF_DECLARE(mtk_mt6577, "mediatek,mt6577-timer", mtk_timer_init);

2
drivers/clocksource/mxs_timer.c
View File

@ -293,4 +293,4 @@ static int __init mxs_timer_init(struct device_node *np)
return setup_irq(irq, &mxs_timer_irq);
}
CLOCKSOURCE_OF_DECLARE(mxs, "fsl,timrot", mxs_timer_init);
TIMER_OF_DECLARE(mxs, "fsl,timrot", mxs_timer_init);

2
drivers/clocksource/nomadik-mtu.c
View File

@ -284,5 +284,5 @@ static int __init nmdk_timer_of_init(struct device_node *node)
return nmdk_timer_init(base, irq, pclk, clk);
}
CLOCKSOURCE_OF_DECLARE(nomadik_mtu, "st,nomadik-mtu",
TIMER_OF_DECLARE(nomadik_mtu, "st,nomadik-mtu",
nmdk_timer_of_init);

2
drivers/clocksource/pxa_timer.c
View File

@ -216,7 +216,7 @@ static int __init pxa_timer_dt_init(struct device_node *np)
return pxa_timer_common_init(irq, clk_get_rate(clk));
}
CLOCKSOURCE_OF_DECLARE(pxa_timer, "marvell,pxa-timer", pxa_timer_dt_init);
TIMER_OF_DECLARE(pxa_timer, "marvell,pxa-timer", pxa_timer_dt_init);
/*
* Legacy timer init for non device-tree boards.

4
drivers/clocksource/qcom-timer.c
View File

@ -254,5 +254,5 @@ static int __init msm_dt_timer_init(struct device_node *np)
return msm_timer_init(freq, 32, irq, !!percpu_offset);
}
CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
TIMER_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
TIMER_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);

2
drivers/clocksource/renesas-ostm.c
View File

@ -262,4 +262,4 @@ static int __init ostm_init(struct device_node *np)
return 0;
}
CLOCKSOURCE_OF_DECLARE(ostm, "renesas,ostm", ostm_init);
TIMER_OF_DECLARE(ostm, "renesas,ostm", ostm_init);

4
drivers/clocksource/rockchip_timer.c
View File

@ -303,5 +303,5 @@ static int __init rk_timer_init(struct device_node *np)
return -EINVAL;
}
CLOCKSOURCE_OF_DECLARE(rk3288_timer, "rockchip,rk3288-timer", rk_timer_init);
CLOCKSOURCE_OF_DECLARE(rk3399_timer, "rockchip,rk3399-timer", rk_timer_init);
TIMER_OF_DECLARE(rk3288_timer, "rockchip,rk3288-timer", rk_timer_init);
TIMER_OF_DECLARE(rk3399_timer, "rockchip,rk3399-timer", rk_timer_init);

10
drivers/clocksource/samsung_pwm_timer.c
View File

@ -418,7 +418,7 @@ void __init samsung_pwm_clocksource_init(void __iomem *base,
_samsung_pwm_clocksource_init();
}
#ifdef CONFIG_CLKSRC_OF
#ifdef CONFIG_TIMER_OF
static int __init samsung_pwm_alloc(struct device_node *np,
const struct samsung_pwm_variant *variant)
{
@ -466,7 +466,7 @@ static int __init s3c2410_pwm_clocksource_init(struct device_node *np)
{
return samsung_pwm_alloc(np, &s3c24xx_variant);
}
CLOCKSOURCE_OF_DECLARE(s3c2410_pwm, "samsung,s3c2410-pwm", s3c2410_pwm_clocksource_init);
TIMER_OF_DECLARE(s3c2410_pwm, "samsung,s3c2410-pwm", s3c2410_pwm_clocksource_init);
static const struct samsung_pwm_variant s3c64xx_variant = {
.bits = 32,
@ -479,7 +479,7 @@ static int __init s3c64xx_pwm_clocksource_init(struct device_node *np)
{
return samsung_pwm_alloc(np, &s3c64xx_variant);
}
CLOCKSOURCE_OF_DECLARE(s3c6400_pwm, "samsung,s3c6400-pwm", s3c64xx_pwm_clocksource_init);
TIMER_OF_DECLARE(s3c6400_pwm, "samsung,s3c6400-pwm", s3c64xx_pwm_clocksource_init);
static const struct samsung_pwm_variant s5p64x0_variant = {
.bits = 32,
@ -492,7 +492,7 @@ static int __init s5p64x0_pwm_clocksource_init(struct device_node *np)
{
return samsung_pwm_alloc(np, &s5p64x0_variant);
}
CLOCKSOURCE_OF_DECLARE(s5p6440_pwm, "samsung,s5p6440-pwm", s5p64x0_pwm_clocksource_init);
TIMER_OF_DECLARE(s5p6440_pwm, "samsung,s5p6440-pwm", s5p64x0_pwm_clocksource_init);
static const struct samsung_pwm_variant s5p_variant = {
.bits = 32,
@ -505,5 +505,5 @@ static int __init s5p_pwm_clocksource_init(struct device_node *np)
{
return samsung_pwm_alloc(np, &s5p_variant);
}
CLOCKSOURCE_OF_DECLARE(s5pc100_pwm, "samsung,s5pc100-pwm", s5p_pwm_clocksource_init);
TIMER_OF_DECLARE(s5pc100_pwm, "samsung,s5pc100-pwm", s5p_pwm_clocksource_init);
#endif

2
drivers/clocksource/sun4i_timer.c
View File

@ -233,5 +233,5 @@ static int __init sun4i_timer_init(struct device_node *node)
return ret;
}
CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
sun4i_timer_init);

2
drivers/clocksource/tango_xtal.c
View File

@ -53,4 +53,4 @@ static int __init tango_clocksource_init(struct device_node *np)
return 0;
}
CLOCKSOURCE_OF_DECLARE(tango, "sigma,tick-counter", tango_clocksource_init);
TIMER_OF_DECLARE(tango, "sigma,tick-counter", tango_clocksource_init);

51
drivers/clocksource/tcb_clksrc.c
View File

@ -9,6 +9,7 @@
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/syscore_ops.h>
#include <linux/atmel_tc.h>
@ -40,6 +41,14 @@
*/
static void __iomem *tcaddr;
static struct
{
u32 cmr;
u32 imr;
u32 rc;
bool clken;
} tcb_cache[3];
static u32 bmr_cache;
static u64 tc_get_cycles(struct clocksource *cs)
{
@ -61,12 +70,54 @@ static u64 tc_get_cycles32(struct clocksource *cs)
return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
}
void tc_clksrc_suspend(struct clocksource *cs)
{
int i;
for (i = 0; i < ARRAY_SIZE(tcb_cache); i++) {
tcb_cache[i].cmr = readl(tcaddr + ATMEL_TC_REG(i, CMR));
tcb_cache[i].imr = readl(tcaddr + ATMEL_TC_REG(i, IMR));
tcb_cache[i].rc = readl(tcaddr + ATMEL_TC_REG(i, RC));
tcb_cache[i].clken = !!(readl(tcaddr + ATMEL_TC_REG(i, SR)) &
ATMEL_TC_CLKSTA);
}
bmr_cache = readl(tcaddr + ATMEL_TC_BMR);
}
void tc_clksrc_resume(struct clocksource *cs)
{
int i;
for (i = 0; i < ARRAY_SIZE(tcb_cache); i++) {
/* Restore registers for the channel, RA and RB are not used */
writel(tcb_cache[i].cmr, tcaddr + ATMEL_TC_REG(i, CMR));
writel(tcb_cache[i].rc, tcaddr + ATMEL_TC_REG(i, RC));
writel(0, tcaddr + ATMEL_TC_REG(i, RA));
writel(0, tcaddr + ATMEL_TC_REG(i, RB));
/* Disable all the interrupts */
writel(0xff, tcaddr + ATMEL_TC_REG(i, IDR));
/* Reenable interrupts that were enabled before suspending */
writel(tcb_cache[i].imr, tcaddr + ATMEL_TC_REG(i, IER));
/* Start the clock if it was used */
if (tcb_cache[i].clken)
writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(i, CCR));
}
/* Dual channel, chain channels */
writel(bmr_cache, tcaddr + ATMEL_TC_BMR);
/* Finally, trigger all the channels*/
writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);
}
static struct clocksource clksrc = {
.name = "tcb_clksrc",
.rating = 200,
.read = tc_get_cycles,
.mask = CLOCKSOURCE_MASK(32),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
.suspend = tc_clksrc_suspend,
.resume = tc_clksrc_resume,
};
#ifdef CONFIG_GENERIC_CLOCKEVENTS

4
drivers/clocksource/tegra20_timer.c
View File

@ -237,7 +237,7 @@ static int __init tegra20_init_timer(struct device_node *np)
return 0;
}
CLOCKSOURCE_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
static int __init tegra20_init_rtc(struct device_node *np)
{
@ -261,4 +261,4 @@ static int __init tegra20_init_rtc(struct device_node *np)
return register_persistent_clock(NULL, tegra_read_persistent_clock64);
}
CLOCKSOURCE_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);

6
drivers/clocksource/time-armada-370-xp.c
View File

@ -351,7 +351,7 @@ static int __init armada_xp_timer_init(struct device_node *np)
return armada_370_xp_timer_common_init(np);
}
CLOCKSOURCE_OF_DECLARE(armada_xp, "marvell,armada-xp-timer",
TIMER_OF_DECLARE(armada_xp, "marvell,armada-xp-timer",
armada_xp_timer_init);
static int __init armada_375_timer_init(struct device_node *np)
@ -389,7 +389,7 @@ static int __init armada_375_timer_init(struct device_node *np)
return armada_370_xp_timer_common_init(np);
}
CLOCKSOURCE_OF_DECLARE(armada_375, "marvell,armada-375-timer",
TIMER_OF_DECLARE(armada_375, "marvell,armada-375-timer",
armada_375_timer_init);
static int __init armada_370_timer_init(struct device_node *np)
@ -412,5 +412,5 @@ static int __init armada_370_timer_init(struct device_node *np)
return armada_370_xp_timer_common_init(np);
}
CLOCKSOURCE_OF_DECLARE(armada_370, "marvell,armada-370-timer",
TIMER_OF_DECLARE(armada_370, "marvell,armada-370-timer",
armada_370_timer_init);

4
drivers/clocksource/time-efm32.c
View File

@ -283,5 +283,5 @@ static int __init efm32_timer_init(struct device_node *np)
return ret;
}
CLOCKSOURCE_OF_DECLARE(efm32compat, "efm32,timer", efm32_timer_init);
CLOCKSOURCE_OF_DECLARE(efm32, "energymicro,efm32-timer", efm32_timer_init);
TIMER_OF_DECLARE(efm32compat, "efm32,timer", efm32_timer_init);
TIMER_OF_DECLARE(efm32, "energymicro,efm32-timer", efm32_timer_init);

2
drivers/clocksource/time-lpc32xx.c
View File

@ -311,4 +311,4 @@ static int __init lpc32xx_timer_init(struct device_node *np)
return ret;
}
CLOCKSOURCE_OF_DECLARE(lpc32xx_timer, "nxp,lpc3220-timer", lpc32xx_timer_init);
TIMER_OF_DECLARE(lpc32xx_timer, "nxp,lpc3220-timer", lpc32xx_timer_init);

2
drivers/clocksource/time-orion.c
View File

@ -189,4 +189,4 @@ static int __init orion_timer_init(struct device_node *np)
return 0;
}
CLOCKSOURCE_OF_DECLARE(orion_timer, "marvell,orion-timer", orion_timer_init);
TIMER_OF_DECLARE(orion_timer, "marvell,orion-timer", orion_timer_init);

2
drivers/clocksource/time-pistachio.c
View File

@ -214,5 +214,5 @@ static int __init pistachio_clksrc_of_init(struct device_node *node)
sched_clock_register(pistachio_read_sched_clock, 32, rate);
return clocksource_register_hz(&pcs_gpt.cs, rate);
}
CLOCKSOURCE_OF_DECLARE(pistachio_gptimer, "img,pistachio-gptimer",
TIMER_OF_DECLARE(pistachio_gptimer, "img,pistachio-gptimer",
pistachio_clksrc_of_init);

2
drivers/clocksource/timer-atlas7.c
View File

@ -283,4 +283,4 @@ static int __init sirfsoc_of_timer_init(struct device_node *np)
return sirfsoc_atlas7_timer_init(np);
}
CLOCKSOURCE_OF_DECLARE(sirfsoc_atlas7_timer, "sirf,atlas7-tick", sirfsoc_of_timer_init);
TIMER_OF_DECLARE(sirfsoc_atlas7_timer, "sirf,atlas7-tick", sirfsoc_of_timer_init);

2
drivers/clocksource/timer-atmel-pit.c
View File

@ -255,5 +255,5 @@ static int __init at91sam926x_pit_dt_init(struct device_node *node)
return 0;
}
CLOCKSOURCE_OF_DECLARE(at91sam926x_pit, "atmel,at91sam9260-pit",
TIMER_OF_DECLARE(at91sam926x_pit, "atmel,at91sam9260-pit",
at91sam926x_pit_dt_init);

2
drivers/clocksource/timer-atmel-st.c
View File

@ -260,5 +260,5 @@ static int __init atmel_st_timer_init(struct device_node *node)
/* register clocksource */
return clocksource_register_hz(&clk32k, sclk_rate);
}
CLOCKSOURCE_OF_DECLARE(atmel_st_timer, "atmel,at91rm9200-st",
TIMER_OF_DECLARE(atmel_st_timer, "atmel,at91rm9200-st",
atmel_st_timer_init);

2
drivers/clocksource/timer-digicolor.c
View File

@ -203,5 +203,5 @@ static int __init digicolor_timer_init(struct device_node *node)
return 0;
}
CLOCKSOURCE_OF_DECLARE(conexant_digicolor, "cnxt,cx92755-timer",
TIMER_OF_DECLARE(conexant_digicolor, "cnxt,cx92755-timer",
digicolor_timer_init);

496
drivers/clocksource/timer-fttmr010.c
View File

@ -11,12 +11,13 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/sched_clock.h>
#include <linux/clk.h>
#include <linux/slab.h>
#include <linux/bitops.h>
#include <linux/delay.h>
/*
* Register definitions for the timers
@ -37,267 +38,368 @@
#define TIMER_INTR_STATE (0x34)
#define TIMER_INTR_MASK (0x38)
#define TIMER_1_CR_ENABLE (1 << 0)
#define TIMER_1_CR_CLOCK (1 << 1)
#define TIMER_1_CR_INT (1 << 2)
#define TIMER_2_CR_ENABLE (1 << 3)
#define TIMER_2_CR_CLOCK (1 << 4)
#define TIMER_2_CR_INT (1 << 5)
#define TIMER_3_CR_ENABLE (1 << 6)
#define TIMER_3_CR_CLOCK (1 << 7)
#define TIMER_3_CR_INT (1 << 8)
#define TIMER_1_CR_UPDOWN (1 << 9)
#define TIMER_2_CR_UPDOWN (1 << 10)
#define TIMER_3_CR_UPDOWN (1 << 11)
#define TIMER_DEFAULT_FLAGS (TIMER_1_CR_UPDOWN | \
TIMER_3_CR_ENABLE | \
TIMER_3_CR_UPDOWN)
#define TIMER_1_CR_ENABLE BIT(0)
#define TIMER_1_CR_CLOCK BIT(1)
#define TIMER_1_CR_INT BIT(2)
#define TIMER_2_CR_ENABLE BIT(3)
#define TIMER_2_CR_CLOCK BIT(4)
#define TIMER_2_CR_INT BIT(5)
#define TIMER_3_CR_ENABLE BIT(6)
#define TIMER_3_CR_CLOCK BIT(7)
#define TIMER_3_CR_INT BIT(8)
#define TIMER_1_CR_UPDOWN BIT(9)
#define TIMER_2_CR_UPDOWN BIT(10)
#define TIMER_3_CR_UPDOWN BIT(11)
#define TIMER_1_INT_MATCH1 (1 << 0)
#define TIMER_1_INT_MATCH2 (1 << 1)
#define TIMER_1_INT_OVERFLOW (1 << 2)
#define TIMER_2_INT_MATCH1 (1 << 3)
#define TIMER_2_INT_MATCH2 (1 << 4)
#define TIMER_2_INT_OVERFLOW (1 << 5)
#define TIMER_3_INT_MATCH1 (1 << 6)
#define TIMER_3_INT_MATCH2 (1 << 7)
#define TIMER_3_INT_OVERFLOW (1 << 8)
/*
* The Aspeed AST2400 moves bits around in the control register
* and lacks bits for setting the timer to count upwards.
*/
#define TIMER_1_CR_ASPEED_ENABLE BIT(0)
#define TIMER_1_CR_ASPEED_CLOCK BIT(1)
#define TIMER_1_CR_ASPEED_INT BIT(2)
#define TIMER_2_CR_ASPEED_ENABLE BIT(4)
#define TIMER_2_CR_ASPEED_CLOCK BIT(5)
#define TIMER_2_CR_ASPEED_INT BIT(6)
#define TIMER_3_CR_ASPEED_ENABLE BIT(8)
#define TIMER_3_CR_ASPEED_CLOCK BIT(9)
#define TIMER_3_CR_ASPEED_INT BIT(10)
#define TIMER_1_INT_MATCH1 BIT(0)
#define TIMER_1_INT_MATCH2 BIT(1)
#define TIMER_1_INT_OVERFLOW BIT(2)
#define TIMER_2_INT_MATCH1 BIT(3)
#define TIMER_2_INT_MATCH2 BIT(4)
#define TIMER_2_INT_OVERFLOW BIT(5)
#define TIMER_3_INT_MATCH1 BIT(6)
#define TIMER_3_INT_MATCH2 BIT(7)
#define TIMER_3_INT_OVERFLOW BIT(8)
#define TIMER_INT_ALL_MASK 0x1ff
static unsigned int tick_rate;
static void __iomem *base;
struct fttmr010 {
void __iomem *base;
unsigned int tick_rate;
bool count_down;
u32 t1_enable_val;
struct clock_event_device clkevt;
#ifdef CONFIG_ARM
struct delay_timer delay_timer;
#endif
};
static u64 notrace fttmr010_read_sched_clock(void)
/*
* A local singleton used by sched_clock and delay timer reads, which are
* fast and stateless
*/
static struct fttmr010 *local_fttmr;
static inline struct fttmr010 *to_fttmr010(struct clock_event_device *evt)
{
return readl(base + TIMER3_COUNT);
return container_of(evt, struct fttmr010, clkevt);
}
static unsigned long fttmr010_read_current_timer_up(void)
{
return readl(local_fttmr->base + TIMER2_COUNT);
}
static unsigned long fttmr010_read_current_timer_down(void)
{
return ~readl(local_fttmr->base + TIMER2_COUNT);
}
static u64 notrace fttmr010_read_sched_clock_up(void)
{
return fttmr010_read_current_timer_up();
}
static u64 notrace fttmr010_read_sched_clock_down(void)
{
return fttmr010_read_current_timer_down();
}
static int fttmr010_timer_set_next_event(unsigned long cycles,
struct clock_event_device *evt)
{
struct fttmr010 *fttmr010 = to_fttmr010(evt);
u32 cr;
/* Setup the match register */
cr = readl(base + TIMER1_COUNT);
writel(cr + cycles, base + TIMER1_MATCH1);
if (readl(base + TIMER1_COUNT) - cr > cycles)
return -ETIME;
/* Stop */
cr = readl(fttmr010->base + TIMER_CR);
cr &= ~fttmr010->t1_enable_val;
writel(cr, fttmr010->base + TIMER_CR);
/* Setup the match register forward/backward in time */
cr = readl(fttmr010->base + TIMER1_COUNT);
if (fttmr010->count_down)
cr -= cycles;
else
cr += cycles;
writel(cr, fttmr010->base + TIMER1_MATCH1);
/* Start */
cr = readl(fttmr010->base + TIMER_CR);
cr |= fttmr010->t1_enable_val;
writel(cr, fttmr010->base + TIMER_CR);
return 0;
}
static int fttmr010_timer_shutdown(struct clock_event_device *evt)
{
struct fttmr010 *fttmr010 = to_fttmr010(evt);
u32 cr;
/*
* Disable also for oneshot: the set_next() call will arm the timer
* instead.
*/
/* Stop timer and interrupt. */
cr = readl(base + TIMER_CR);
cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT);
writel(cr, base + TIMER_CR);
/* Stop */
cr = readl(fttmr010->base + TIMER_CR);
cr &= ~fttmr010->t1_enable_val;
writel(cr, fttmr010->base + TIMER_CR);
/* Setup counter start from 0 */
writel(0, base + TIMER1_COUNT);
writel(0, base + TIMER1_LOAD);
return 0;
}
/* enable interrupt */
cr = readl(base + TIMER_INTR_MASK);
static int fttmr010_timer_set_oneshot(struct clock_event_device *evt)
{
struct fttmr010 *fttmr010 = to_fttmr010(evt);
u32 cr;
/* Stop */
cr = readl(fttmr010->base + TIMER_CR);
cr &= ~fttmr010->t1_enable_val;
writel(cr, fttmr010->base + TIMER_CR);
/* Setup counter start from 0 or ~0 */
writel(0, fttmr010->base + TIMER1_COUNT);
if (fttmr010->count_down)
writel(~0, fttmr010->base + TIMER1_LOAD);
else
writel(0, fttmr010->base + TIMER1_LOAD);
/* Enable interrupt */
cr = readl(fttmr010->base + TIMER_INTR_MASK);
cr &= ~(TIMER_1_INT_OVERFLOW | TIMER_1_INT_MATCH2);
cr |= TIMER_1_INT_MATCH1;
writel(cr, base + TIMER_INTR_MASK);
/* start the timer */
cr = readl(base + TIMER_CR);
cr |= TIMER_1_CR_ENABLE;
writel(cr, base + TIMER_CR);
writel(cr, fttmr010->base + TIMER_INTR_MASK);
return 0;
}
static int fttmr010_timer_set_periodic(struct clock_event_device *evt)
{
u32 period = DIV_ROUND_CLOSEST(tick_rate, HZ);
struct fttmr010 *fttmr010 = to_fttmr010(evt);
u32 period = DIV_ROUND_CLOSEST(fttmr010->tick_rate, HZ);
u32 cr;
/* Stop timer and interrupt */
cr = readl(base + TIMER_CR);
cr &= ~(TIMER_1_CR_ENABLE | TIMER_1_CR_INT);
writel(cr, base + TIMER_CR);
/* Stop */
cr = readl(fttmr010->base + TIMER_CR);
cr &= ~fttmr010->t1_enable_val;
writel(cr, fttmr010->base + TIMER_CR);
/* Setup timer to fire at 1/HT intervals. */
cr = 0xffffffff - (period - 1);
writel(cr, base + TIMER1_COUNT);
writel(cr, base + TIMER1_LOAD);
/* Setup timer to fire at 1/HZ intervals. */
if (fttmr010->count_down) {
writel(period, fttmr010->base + TIMER1_LOAD);
writel(0, fttmr010->base + TIMER1_MATCH1);
} else {
cr = 0xffffffff - (period - 1);
writel(cr, fttmr010->base + TIMER1_COUNT);
writel(cr, fttmr010->base + TIMER1_LOAD);
/* enable interrupt on overflow */
cr = readl(base + TIMER_INTR_MASK);
cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2);
cr |= TIMER_1_INT_OVERFLOW;
writel(cr, base + TIMER_INTR_MASK);
/* Enable interrupt on overflow */
cr = readl(fttmr010->base + TIMER_INTR_MASK);
cr &= ~(TIMER_1_INT_MATCH1 | TIMER_1_INT_MATCH2);
cr |= TIMER_1_INT_OVERFLOW;
writel(cr, fttmr010->base + TIMER_INTR_MASK);
}
/* Start the timer */
cr = readl(base + TIMER_CR);
cr |= TIMER_1_CR_ENABLE;
cr |= TIMER_1_CR_INT;
writel(cr, base + TIMER_CR);
cr = readl(fttmr010->base + TIMER_CR);
cr |= fttmr010->t1_enable_val;
writel(cr, fttmr010->base + TIMER_CR);
return 0;
}
/* Use TIMER1 as clock event */
static struct clock_event_device fttmr010_clockevent = {
.name = "TIMER1",
/* Reasonably fast and accurate clock event */
.rating = 300,
.shift = 32,
.features = CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_ONESHOT,
.set_next_event = fttmr010_timer_set_next_event,
.set_state_shutdown = fttmr010_timer_shutdown,
.set_state_periodic = fttmr010_timer_set_periodic,
.set_state_oneshot = fttmr010_timer_shutdown,
.tick_resume = fttmr010_timer_shutdown,
};
/*
* IRQ handler for the timer
*/
static irqreturn_t fttmr010_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *evt = &fttmr010_clockevent;
struct clock_event_device *evt = dev_id;
evt->event_handler(evt);
return IRQ_HANDLED;
}
static struct irqaction fttmr010_timer_irq = {
.name = "Faraday FTTMR010 Timer Tick",
.flags = IRQF_TIMER,
.handler = fttmr010_timer_interrupt,
};
static int __init fttmr010_timer_common_init(struct device_node *np)
static int __init fttmr010_common_init(struct device_node *np, bool is_aspeed)
{
struct fttmr010 *fttmr010;
int irq;
struct clk *clk;
int ret;
u32 val;
base = of_iomap(np, 0);
if (!base) {
pr_err("Can't remap registers");
return -ENXIO;
}
/* IRQ for timer 1 */
irq = irq_of_parse_and_map(np, 0);
if (irq <= 0) {
pr_err("Can't parse IRQ");
return -EINVAL;
}
/*
* Reset the interrupt mask and status
*/
writel(TIMER_INT_ALL_MASK, base + TIMER_INTR_MASK);
writel(0, base + TIMER_INTR_STATE);
writel(TIMER_DEFAULT_FLAGS, base + TIMER_CR);
/*
* Setup free-running clocksource timer (interrupts
* disabled.)
*/
writel(0, base + TIMER3_COUNT);
writel(0, base + TIMER3_LOAD);
writel(0, base + TIMER3_MATCH1);
writel(0, base + TIMER3_MATCH2);
clocksource_mmio_init(base + TIMER3_COUNT,
"fttmr010_clocksource", tick_rate,
300, 32, clocksource_mmio_readl_up);
sched_clock_register(fttmr010_read_sched_clock, 32, tick_rate);
/*
* Setup clockevent timer (interrupt-driven.)
*/
writel(0, base + TIMER1_COUNT);
writel(0, base + TIMER1_LOAD);
writel(0, base + TIMER1_MATCH1);
writel(0, base + TIMER1_MATCH2);
setup_irq(irq, &fttmr010_timer_irq);
fttmr010_clockevent.cpumask = cpumask_of(0);
clockevents_config_and_register(&fttmr010_clockevent, tick_rate,
1, 0xffffffff);
return 0;
}
static int __init fttmr010_timer_of_init(struct device_node *np)
{
/*
* These implementations require a clock reference.
* FIXME: we currently only support clocking using PCLK
* and using EXTCLK is not supported in the driver.
*/
struct clk *clk;
clk = of_clk_get_by_name(np, "PCLK");
if (IS_ERR(clk)) {
pr_err("could not get PCLK");
pr_err("could not get PCLK\n");
return PTR_ERR(clk);
}
tick_rate = clk_get_rate(clk);
return fttmr010_timer_common_init(np);
}
CLOCKSOURCE_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_of_init);
/*
* Gemini-specific: relevant registers in the global syscon
*/
#define GLOBAL_STATUS 0x04
#define CPU_AHB_RATIO_MASK (0x3 << 18)
#define CPU_AHB_1_1 (0x0 << 18)
#define CPU_AHB_3_2 (0x1 << 18)
#define CPU_AHB_24_13 (0x2 << 18)
#define CPU_AHB_2_1 (0x3 << 18)
#define REG_TO_AHB_SPEED(reg) ((((reg) >> 15) & 0x7) * 10 + 130)
static int __init gemini_timer_of_init(struct device_node *np)
{
static struct regmap *map;
int ret;
u32 val;
map = syscon_regmap_lookup_by_phandle(np, "syscon");
if (IS_ERR(map)) {
pr_err("Can't get regmap for syscon handle\n");
return -ENODEV;
}
ret = regmap_read(map, GLOBAL_STATUS, &val);
ret = clk_prepare_enable(clk);
if (ret) {
pr_err("Can't read syscon status register\n");
return -ENXIO;
pr_err("failed to enable PCLK\n");
return ret;
}
tick_rate = REG_TO_AHB_SPEED(val) * 1000000;
pr_info("Bus: %dMHz ", tick_rate / 1000000);
fttmr010 = kzalloc(sizeof(*fttmr010), GFP_KERNEL);
if (!fttmr010) {
ret = -ENOMEM;
goto out_disable_clock;
}
fttmr010->tick_rate = clk_get_rate(clk);
tick_rate /= 6; /* APB bus run AHB*(1/6) */
switch (val & CPU_AHB_RATIO_MASK) {
case CPU_AHB_1_1:
pr_cont("(1/1)\n");
break;
case CPU_AHB_3_2:
pr_cont("(3/2)\n");
break;
case CPU_AHB_24_13:
pr_cont("(24/13)\n");
break;
case CPU_AHB_2_1:
pr_cont("(2/1)\n");
break;
fttmr010->base = of_iomap(np, 0);
if (!fttmr010->base) {
pr_err("Can't remap registers");
ret = -ENXIO;
goto out_free;
}
/* IRQ for timer 1 */
irq = irq_of_parse_and_map(np, 0);
if (irq <= 0) {
pr_err("Can't parse IRQ");
ret = -EINVAL;
goto out_unmap;
}
return fttmr010_timer_common_init(np);
/*
* The Aspeed AST2400 moves bits around in the control register,
* otherwise it works the same.
*/
if (is_aspeed) {
fttmr010->t1_enable_val = TIMER_1_CR_ASPEED_ENABLE |
TIMER_1_CR_ASPEED_INT;
/* Downward not available */
fttmr010->count_down = true;
} else {
fttmr010->t1_enable_val = TIMER_1_CR_ENABLE | TIMER_1_CR_INT;
}
/*
* Reset the interrupt mask and status
*/
writel(TIMER_INT_ALL_MASK, fttmr010->base + TIMER_INTR_MASK);
writel(0, fttmr010->base + TIMER_INTR_STATE);
/*
* Enable timer 1 count up, timer 2 count up, except on Aspeed,
* where everything just counts down.
*/
if (is_aspeed)
val = TIMER_2_CR_ASPEED_ENABLE;
else {
val = TIMER_2_CR_ENABLE;
if (!fttmr010->count_down)
val |= TIMER_1_CR_UPDOWN | TIMER_2_CR_UPDOWN;
}
writel(val, fttmr010->base + TIMER_CR);
/*
* Setup free-running clocksource timer (interrupts
* disabled.)
*/
local_fttmr = fttmr010;
writel(0, fttmr010->base + TIMER2_COUNT);
writel(0, fttmr010->base + TIMER2_MATCH1);
writel(0, fttmr010->base + TIMER2_MATCH2);
if (fttmr010->count_down) {
writel(~0, fttmr010->base + TIMER2_LOAD);
clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
"FTTMR010-TIMER2",
fttmr010->tick_rate,
300, 32, clocksource_mmio_readl_down);
sched_clock_register(fttmr010_read_sched_clock_down, 32,
fttmr010->tick_rate);
} else {
writel(0, fttmr010->base + TIMER2_LOAD);
clocksource_mmio_init(fttmr010->base + TIMER2_COUNT,
"FTTMR010-TIMER2",
fttmr010->tick_rate,
300, 32, clocksource_mmio_readl_up);
sched_clock_register(fttmr010_read_sched_clock_up, 32,
fttmr010->tick_rate);
}
/*
* Setup clockevent timer (interrupt-driven) on timer 1.
*/
writel(0, fttmr010->base + TIMER1_COUNT);
writel(0, fttmr010->base + TIMER1_LOAD);
writel(0, fttmr010->base + TIMER1_MATCH1);
writel(0, fttmr010->base + TIMER1_MATCH2);
ret = request_irq(irq, fttmr010_timer_interrupt, IRQF_TIMER,
"FTTMR010-TIMER1", &fttmr010->clkevt);
if (ret) {
pr_err("FTTMR010-TIMER1 no IRQ\n");
goto out_unmap;
}
fttmr010->clkevt.name = "FTTMR010-TIMER1";
/* Reasonably fast and accurate clock event */
fttmr010->clkevt.rating = 300;
fttmr010->clkevt.features = CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_ONESHOT;
fttmr010->clkevt.set_next_event = fttmr010_timer_set_next_event;
fttmr010->clkevt.set_state_shutdown = fttmr010_timer_shutdown;
fttmr010->clkevt.set_state_periodic = fttmr010_timer_set_periodic;
fttmr010->clkevt.set_state_oneshot = fttmr010_timer_set_oneshot;
fttmr010->clkevt.tick_resume = fttmr010_timer_shutdown;
fttmr010->clkevt.cpumask = cpumask_of(0);
fttmr010->clkevt.irq = irq;
clockevents_config_and_register(&fttmr010->clkevt,
fttmr010->tick_rate,
1, 0xffffffff);
#ifdef CONFIG_ARM
/* Also use this timer for delays */
if (fttmr010->count_down)
fttmr010->delay_timer.read_current_timer =
fttmr010_read_current_timer_down;
else
fttmr010->delay_timer.read_current_timer =
fttmr010_read_current_timer_up;
fttmr010->delay_timer.freq = fttmr010->tick_rate;
register_current_timer_delay(&fttmr010->delay_timer);
#endif
return 0;
out_unmap:
iounmap(fttmr010->base);
out_free:
kfree(fttmr010);
out_disable_clock:
clk_disable_unprepare(clk);
return ret;
}
CLOCKSOURCE_OF_DECLARE(gemini, "cortina,gemini-timer", gemini_timer_of_init);
static __init int aspeed_timer_init(struct device_node *np)
{
return fttmr010_common_init(np, true);
}
static __init int fttmr010_timer_init(struct device_node *np)
{
return fttmr010_common_init(np, false);
}
TIMER_OF_DECLARE(fttmr010, "faraday,fttmr010", fttmr010_timer_init);
TIMER_OF_DECLARE(gemini, "cortina,gemini-timer", fttmr010_timer_init);
TIMER_OF_DECLARE(moxart, "moxa,moxart-timer", fttmr010_timer_init);
TIMER_OF_DECLARE(ast2400, "aspeed,ast2400-timer", aspeed_timer_init);
TIMER_OF_DECLARE(ast2500, "aspeed,ast2500-timer", aspeed_timer_init);

24
drivers/clocksource/timer-imx-gpt.c
View File

@ -545,15 +545,15 @@ static int __init imx6dl_timer_init_dt(struct device_node *np)
return mxc_timer_init_dt(np, GPT_TYPE_IMX6DL);
}
CLOCKSOURCE_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx27_timer, "fsl,imx27-gpt", imx21_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt);
CLOCKSOURCE_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt);
TIMER_OF_DECLARE(imx1_timer, "fsl,imx1-gpt", imx1_timer_init_dt);
TIMER_OF_DECLARE(imx21_timer, "fsl,imx21-gpt", imx21_timer_init_dt);
TIMER_OF_DECLARE(imx27_timer, "fsl,imx27-gpt", imx21_timer_init_dt);
TIMER_OF_DECLARE(imx31_timer, "fsl,imx31-gpt", imx31_timer_init_dt);
TIMER_OF_DECLARE(imx25_timer, "fsl,imx25-gpt", imx31_timer_init_dt);
TIMER_OF_DECLARE(imx50_timer, "fsl,imx50-gpt", imx31_timer_init_dt);
TIMER_OF_DECLARE(imx51_timer, "fsl,imx51-gpt", imx31_timer_init_dt);
TIMER_OF_DECLARE(imx53_timer, "fsl,imx53-gpt", imx31_timer_init_dt);
TIMER_OF_DECLARE(imx6q_timer, "fsl,imx6q-gpt", imx31_timer_init_dt);
TIMER_OF_DECLARE(imx6dl_timer, "fsl,imx6dl-gpt", imx6dl_timer_init_dt);
TIMER_OF_DECLARE(imx6sl_timer, "fsl,imx6sl-gpt", imx6dl_timer_init_dt);
TIMER_OF_DECLARE(imx6sx_timer, "fsl,imx6sx-gpt", imx6dl_timer_init_dt);

2
drivers/clocksource/timer-integrator-ap.c
View File

@ -232,5 +232,5 @@ static int __init integrator_ap_timer_init_of(struct device_node *node)
return 0;
}
CLOCKSOURCE_OF_DECLARE(integrator_ap_timer, "arm,integrator-timer",
TIMER_OF_DECLARE(integrator_ap_timer, "arm,integrator-timer",
integrator_ap_timer_init_of);

2
drivers/clocksource/timer-keystone.c
View File

@ -226,5 +226,5 @@ static int __init keystone_timer_init(struct device_node *np)
return error;
}
CLOCKSOURCE_OF_DECLARE(keystone_timer, "ti,keystone-timer",
TIMER_OF_DECLARE(keystone_timer, "ti,keystone-timer",
keystone_timer_init);

6
drivers/clocksource/timer-nps.c
View File

@ -110,9 +110,9 @@ static int __init nps_setup_clocksource(struct device_node *node)
return ret;
}
CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
TIMER_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
nps_setup_clocksource);
CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clk_src, "ezchip,nps400-timer1",
TIMER_OF_DECLARE(ezchip_nps400_clk_src, "ezchip,nps400-timer1",
nps_setup_clocksource);
#ifdef CONFIG_EZNPS_MTM_EXT
@ -279,6 +279,6 @@ static int __init nps_setup_clockevent(struct device_node *node)
return 0;
}
CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clk_evt, "ezchip,nps400-timer0",
TIMER_OF_DECLARE(ezchip_nps400_clk_evt, "ezchip,nps400-timer0",
nps_setup_clockevent);
#endif /* CONFIG_EZNPS_MTM_EXT */

172
drivers/clocksource/timer-of.c Normal file
View File

@ -0,0 +1,172 @@
/*
* Copyright (c) 2017, Linaro Ltd. All rights reserved.
*
* Author: Daniel Lezcano <daniel.lezcano@linaro.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/slab.h>
#include "timer-of.h"
static __init void timer_irq_exit(struct of_timer_irq *of_irq)
{
struct timer_of *to = container_of(of_irq, struct timer_of, of_irq);
struct clock_event_device *clkevt = &to->clkevt;
of_irq->percpu ? free_percpu_irq(of_irq->irq, clkevt) :
free_irq(of_irq->irq, clkevt);
}
static __init int timer_irq_init(struct device_node *np,
struct of_timer_irq *of_irq)
{
int ret;
struct timer_of *to = container_of(of_irq, struct timer_of, of_irq);
struct clock_event_device *clkevt = &to->clkevt;
of_irq->irq = of_irq->name ? of_irq_get_byname(np, of_irq->name):
irq_of_parse_and_map(np, of_irq->index);
if (!of_irq->irq) {
pr_err("Failed to map interrupt for %s\n", np->full_name);
return -EINVAL;
}
ret = of_irq->percpu ?
request_percpu_irq(of_irq->irq, of_irq->handler,
np->full_name, clkevt) :
request_irq(of_irq->irq, of_irq->handler,
of_irq->flags ? of_irq->flags : IRQF_TIMER,
np->full_name, clkevt);
if (ret) {
pr_err("Failed to request irq %d for %s\n", of_irq->irq,
np->full_name);
return ret;
}
clkevt->irq = of_irq->irq;
return 0;
}
static __init void timer_clk_exit(struct of_timer_clk *of_clk)
{
of_clk->rate = 0;
clk_disable_unprepare(of_clk->clk);
clk_put(of_clk->clk);
}
static __init int timer_clk_init(struct device_node *np,
struct of_timer_clk *of_clk)
{
int ret;
of_clk->clk = of_clk->name ? of_clk_get_by_name(np, of_clk->name) :
of_clk_get(np, of_clk->index);
if (IS_ERR(of_clk->clk)) {
pr_err("Failed to get clock for %s\n", np->full_name);
return PTR_ERR(of_clk->clk);
}
ret = clk_prepare_enable(of_clk->clk);
if (ret) {
pr_err("Failed for enable clock for %s\n", np->full_name);
goto out_clk_put;
}
of_clk->rate = clk_get_rate(of_clk->clk);
if (!of_clk->rate) {
ret = -EINVAL;
pr_err("Failed to get clock rate for %s\n", np->full_name);
goto out_clk_disable;
}
of_clk->period = DIV_ROUND_UP(of_clk->rate, HZ);
out:
return ret;
out_clk_disable:
clk_disable_unprepare(of_clk->clk);
out_clk_put:
clk_put(of_clk->clk);
goto out;
}
static __init void timer_base_exit(struct of_timer_base *of_base)
{
iounmap(of_base->base);
}
static __init int timer_base_init(struct device_node *np,
struct of_timer_base *of_base)
{
const char *name = of_base->name ? of_base->name : np->full_name;
of_base->base = of_io_request_and_map(np, of_base->index, name);
if (of_base->base) {
pr_err("Failed to iomap (%s)\n", name);
return -ENXIO;
}
return 0;
}
int __init timer_of_init(struct device_node *np, struct timer_of *to)
{
int ret;
int flags = 0;
if (to->flags & TIMER_OF_BASE) {
ret = timer_base_init(np, &to->of_base);
if (ret)
goto out_fail;
flags |= TIMER_OF_BASE;
}
if (to->flags & TIMER_OF_CLOCK) {
ret = timer_clk_init(np, &to->of_clk);
if (ret)
goto out_fail;
flags |= TIMER_OF_CLOCK;
}
if (to->flags & TIMER_OF_IRQ) {
ret = timer_irq_init(np, &to->of_irq);
if (ret)
goto out_fail;
flags |= TIMER_OF_IRQ;
}
if (!to->clkevt.name)
to->clkevt.name = np->name;
out:
return ret;
out_fail:
if (flags & TIMER_OF_IRQ)
timer_irq_exit(&to->of_irq);
if (flags & TIMER_OF_CLOCK)
timer_clk_exit(&to->of_clk);
if (flags & TIMER_OF_BASE)
timer_base_exit(&to->of_base);
goto out;
}

69
drivers/clocksource/timer-of.h Normal file
View File

@ -0,0 +1,69 @@
#ifndef __TIMER_OF_H__
#define __TIMER_OF_H__
#include <linux/clockchips.h>
#define TIMER_OF_BASE 0x1
#define TIMER_OF_CLOCK 0x2
#define TIMER_OF_IRQ 0x4
struct of_timer_irq {
int irq;
int index;
int percpu;
const char *name;
unsigned long flags;
irq_handler_t handler;
};
struct of_timer_base {
void __iomem *base;
const char *name;
int index;
};
struct of_timer_clk {
struct clk *clk;
const char *name;
int index;
unsigned long rate;
unsigned long period;
};
struct timer_of {
unsigned int flags;
struct clock_event_device clkevt;
struct of_timer_base of_base;
struct of_timer_irq of_irq;
struct of_timer_clk of_clk;
void *private_data;
};
static inline struct timer_of *to_timer_of(struct clock_event_device *clkevt)
{
return container_of(clkevt, struct timer_of, clkevt);
}
static inline void __iomem *timer_of_base(struct timer_of *to)
{
return to->of_base.base;
}
static inline int timer_of_irq(struct timer_of *to)
{
return to->of_irq.irq;
}
static inline unsigned long timer_of_rate(struct timer_of *to)
{
return to->of_clk.rate;
}
static inline unsigned long timer_of_period(struct timer_of *to)
{
return to->of_clk.period;
}
extern int __init timer_of_init(struct device_node *np,
struct timer_of *to);
#endif

4
drivers/clocksource/timer-oxnas-rps.c
View File

@ -293,7 +293,7 @@ static int __init oxnas_rps_timer_init(struct device_node *np)
return ret;
}
CLOCKSOURCE_OF_DECLARE(ox810se_rps,
TIMER_OF_DECLARE(ox810se_rps,
"oxsemi,ox810se-rps-timer", oxnas_rps_timer_init);
CLOCKSOURCE_OF_DECLARE(ox820_rps,
TIMER_OF_DECLARE(ox820_rps,
"oxsemi,ox820se-rps-timer", oxnas_rps_timer_init);

2
drivers/clocksource/timer-prima2.c
View File

@ -245,5 +245,5 @@ static int __init sirfsoc_prima2_timer_init(struct device_node *np)
return 0;
}
CLOCKSOURCE_OF_DECLARE(sirfsoc_prima2_timer,
TIMER_OF_DECLARE(sirfsoc_prima2_timer,
"sirf,prima2-tick", sirfsoc_prima2_timer_init);

20
drivers/clocksource/clksrc-probe.c → drivers/clocksource/timer-probe.c
View File

@ -19,20 +19,20 @@
#include <linux/of.h>
#include <linux/clocksource.h>
extern struct of_device_id __clksrc_of_table[];
extern struct of_device_id __timer_of_table[];
static const struct of_device_id __clksrc_of_table_sentinel
__used __section(__clksrc_of_table_end);
static const struct of_device_id __timer_of_table_sentinel
__used __section(__timer_of_table_end);
void __init clocksource_probe(void)
void __init timer_probe(void)
{
struct device_node *np;
const struct of_device_id *match;
of_init_fn_1_ret init_func_ret;
unsigned clocksources = 0;
unsigned timers = 0;
int ret;
for_each_matching_node_and_match(np, __clksrc_of_table, &match) {
for_each_matching_node_and_match(np, __timer_of_table, &match) {
if (!of_device_is_available(np))
continue;
@ -45,11 +45,11 @@ void __init clocksource_probe(void)
continue;
}
clocksources++;
timers++;
}
clocksources += acpi_probe_device_table(clksrc);
timers += acpi_probe_device_table(timer);
if (!clocksources)
pr_crit("%s: no matching clocksources found\n", __func__);
if (!timers)
pr_crit("%s: no matching timers found\n", __func__);
}

4
drivers/clocksource/timer-sp804.c
View File

@ -287,7 +287,7 @@ static int __init sp804_of_init(struct device_node *np)
iounmap(base);
return ret;
}
CLOCKSOURCE_OF_DECLARE(sp804, "arm,sp804", sp804_of_init);
TIMER_OF_DECLARE(sp804, "arm,sp804", sp804_of_init);
static int __init integrator_cp_of_init(struct device_node *np)
{
@ -335,4 +335,4 @@ static int __init integrator_cp_of_init(struct device_node *np)
iounmap(base);
return ret;
}
CLOCKSOURCE_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init);
TIMER_OF_DECLARE(intcp, "arm,integrator-cp-timer", integrator_cp_of_init);

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