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ARM: kernel: update __cpu_disable to use cache LoUIS maintenance API

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When a CPU is hotplugged out caches that reside in its power domain
lose their contents and so must be cleaned to the next memory level.

Currently, __cpu_disable calls flush_cache_all() that for new generation
processor like A15/A7 ends up cleaning and invalidating all cache levels
up to Level of Coherency, which includes the unified L2.

This ends up being a waste of cycles since the L2 cache contents are not
lost on power down.

This patch updates __cpu_disable to use the new LoUIS API cache operations.

Acked-by: Nicolas Pitre <nico@linaro.org>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
Lorenzo Pieralisi 2012-09-07 11:09:15 +05:30
parent dbee0c6fb4
commit e6b866e954
1 changed files with 4 additions and 1 deletions
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5
arch/arm/kernel/smp.c
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@ -134,8 +134,11 @@ int __cpu_disable(void)
/*
* Flush user cache and TLB mappings, and then remove this CPU
* from the vm mask set of all processes.
*
* Caches are flushed to the Level of Unification Inner Shareable
* to write-back dirty lines to unified caches shared by all CPUs.
*/
flush_cache_all();
flush_cache_louis();
local_flush_tlb_all();
clear_tasks_mm_cpumask(cpu);