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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-29 22:16:47 +07:00
vmwgfx: Don't write to read-only registers
Signed-off-by: Michel Dänzer <daenzer@vmware.com> Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -195,12 +195,7 @@ struct vmw_private {
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struct vmw_vga_topology_state vga_save[VMWGFX_MAX_DISPLAYS];
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uint32_t vga_width;
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uint32_t vga_height;
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uint32_t vga_depth;
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uint32_t vga_bpp;
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uint32_t vga_pseudo;
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uint32_t vga_red_mask;
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uint32_t vga_green_mask;
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uint32_t vga_blue_mask;
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uint32_t vga_bpl;
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uint32_t vga_pitchlock;
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@ -1001,10 +1001,6 @@ void vmw_kms_write_svga(struct vmw_private *vmw_priv,
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vmw_write(vmw_priv, SVGA_REG_WIDTH, width);
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vmw_write(vmw_priv, SVGA_REG_HEIGHT, height);
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vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bbp);
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vmw_write(vmw_priv, SVGA_REG_DEPTH, depth);
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vmw_write(vmw_priv, SVGA_REG_RED_MASK, 0x00ff0000);
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vmw_write(vmw_priv, SVGA_REG_GREEN_MASK, 0x0000ff00);
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vmw_write(vmw_priv, SVGA_REG_BLUE_MASK, 0x000000ff);
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}
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int vmw_kms_save_vga(struct vmw_private *vmw_priv)
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@ -1014,12 +1010,7 @@ int vmw_kms_save_vga(struct vmw_private *vmw_priv)
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vmw_priv->vga_width = vmw_read(vmw_priv, SVGA_REG_WIDTH);
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vmw_priv->vga_height = vmw_read(vmw_priv, SVGA_REG_HEIGHT);
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vmw_priv->vga_depth = vmw_read(vmw_priv, SVGA_REG_DEPTH);
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vmw_priv->vga_bpp = vmw_read(vmw_priv, SVGA_REG_BITS_PER_PIXEL);
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vmw_priv->vga_pseudo = vmw_read(vmw_priv, SVGA_REG_PSEUDOCOLOR);
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vmw_priv->vga_red_mask = vmw_read(vmw_priv, SVGA_REG_RED_MASK);
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vmw_priv->vga_blue_mask = vmw_read(vmw_priv, SVGA_REG_BLUE_MASK);
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vmw_priv->vga_green_mask = vmw_read(vmw_priv, SVGA_REG_GREEN_MASK);
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if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
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vmw_priv->vga_pitchlock =
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vmw_read(vmw_priv, SVGA_REG_PITCHLOCK);
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@ -1068,12 +1059,7 @@ int vmw_kms_restore_vga(struct vmw_private *vmw_priv)
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vmw_write(vmw_priv, SVGA_REG_WIDTH, vmw_priv->vga_width);
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vmw_write(vmw_priv, SVGA_REG_HEIGHT, vmw_priv->vga_height);
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vmw_write(vmw_priv, SVGA_REG_DEPTH, vmw_priv->vga_depth);
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vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, vmw_priv->vga_bpp);
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vmw_write(vmw_priv, SVGA_REG_PSEUDOCOLOR, vmw_priv->vga_pseudo);
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vmw_write(vmw_priv, SVGA_REG_RED_MASK, vmw_priv->vga_red_mask);
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vmw_write(vmw_priv, SVGA_REG_GREEN_MASK, vmw_priv->vga_green_mask);
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vmw_write(vmw_priv, SVGA_REG_BLUE_MASK, vmw_priv->vga_blue_mask);
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if (vmw_priv->capabilities & SVGA_CAP_PITCHLOCK)
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vmw_write(vmw_priv, SVGA_REG_PITCHLOCK,
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vmw_priv->vga_pitchlock);
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