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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 10:16:41 +07:00
MIPS: BCM63XX: Add basic BCM6328 support
This includes CPU speed, memory size detection and working UART, but lacking the appropriate drivers, no support for attached flash. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Cc: linux-mips@linux-mips.org Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/3951/ Reviewed-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Jonas Gorski
Ralf Baechle
parent
288752a8aa
commit
e5766aea5b
@ -1,6 +1,9 @@
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menu "CPU support"
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depends on BCM63XX
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config BCM63XX_CPU_6328
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bool "support 6328 CPU"
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config BCM63XX_CPU_6338
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bool "support 6338 CPU"
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select HW_HAS_PCI
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@ -708,9 +708,15 @@ void __init board_prom_init(void)
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char cfe_version[32];
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u32 val;
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/* read base address of boot chip select (0) */
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val = bcm_mpi_readl(MPI_CSBASE_REG(0));
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val &= MPI_CSBASE_BASE_MASK;
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/* read base address of boot chip select (0)
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* 6328 does not have MPI but boots from a fixed address
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*/
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if (BCMCPU_IS_6328())
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val = 0x18000000;
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else {
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val = bcm_mpi_readl(MPI_CSBASE_REG(0));
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val &= MPI_CSBASE_BASE_MASK;
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}
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boot_addr = (u8 *)KSEG1ADDR(val);
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/* dump cfe version */
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@ -29,6 +29,14 @@ static u16 bcm63xx_cpu_rev;
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static unsigned int bcm63xx_cpu_freq;
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static unsigned int bcm63xx_memory_size;
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static const unsigned long bcm6328_regs_base[] = {
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__GEN_CPU_REGS_TABLE(6328)
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};
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static const int bcm6328_irqs[] = {
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__GEN_CPU_IRQ_TABLE(6328)
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};
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static const unsigned long bcm6338_regs_base[] = {
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__GEN_CPU_REGS_TABLE(6338)
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};
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@ -99,6 +107,33 @@ unsigned int bcm63xx_get_memory_size(void)
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static unsigned int detect_cpu_clock(void)
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{
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switch (bcm63xx_get_cpu_id()) {
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case BCM6328_CPU_ID:
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{
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unsigned int tmp, mips_pll_fcvo;
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tmp = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
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mips_pll_fcvo = (tmp & STRAPBUS_6328_FCVO_MASK)
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>> STRAPBUS_6328_FCVO_SHIFT;
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switch (mips_pll_fcvo) {
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case 0x12:
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case 0x14:
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case 0x19:
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return 160000000;
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case 0x1c:
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return 192000000;
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case 0x13:
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case 0x15:
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return 200000000;
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case 0x1a:
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return 384000000;
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case 0x16:
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return 400000000;
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default:
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return 320000000;
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}
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}
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case BCM6338_CPU_ID:
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/* BCM6338 has a fixed 240 Mhz frequency */
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return 240000000;
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@ -170,6 +205,9 @@ static unsigned int detect_memory_size(void)
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unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
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u32 val;
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if (BCMCPU_IS_6328())
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return bcm_ddr_readl(DDR_CSEND_REG) << 24;
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if (BCMCPU_IS_6345()) {
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val = bcm_sdram_readl(SDRAM_MBASE_REG);
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return (val * 8 * 1024 * 1024);
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@ -237,6 +275,11 @@ void __init bcm63xx_cpu_init(void)
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u16 chip_id = bcm_readw(BCM_6368_PERF_BASE);
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switch (chip_id) {
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case BCM6328_CPU_ID:
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expected_cpu_id = BCM6328_CPU_ID;
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bcm63xx_regs_base = bcm6328_regs_base;
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bcm63xx_irqs = bcm6328_irqs;
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break;
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case BCM6368_CPU_ID:
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expected_cpu_id = BCM6368_CPU_ID;
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bcm63xx_regs_base = bcm6368_regs_base;
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@ -60,6 +60,12 @@ static int __init bcm63xx_detect_flash_type(void)
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u32 val;
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switch (bcm63xx_get_cpu_id()) {
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case BCM6328_CPU_ID:
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val = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
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if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
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return BCM63XX_FLASH_TYPE_SERIAL;
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else
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return BCM63XX_FLASH_TYPE_NAND;
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case BCM6338_CPU_ID:
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case BCM6345_CPU_ID:
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case BCM6348_CPU_ID:
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@ -87,7 +87,7 @@ int __init bcm63xx_spi_register(void)
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{
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struct clk *periph_clk;
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if (BCMCPU_IS_6345())
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if (BCMCPU_IS_6328() || BCMCPU_IS_6345())
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return -ENODEV;
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periph_clk = clk_get(NULL, "periph");
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@ -27,6 +27,17 @@ static void __internal_irq_unmask_32(unsigned int irq) __maybe_unused;
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static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
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#ifndef BCMCPU_RUNTIME_DETECT
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#ifdef CONFIG_BCM63XX_CPU_6328
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#define irq_stat_reg PERF_IRQSTAT_6328_REG
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#define irq_mask_reg PERF_IRQMASK_6328_REG
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#define irq_bits 64
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#define is_ext_irq_cascaded 1
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#define ext_irq_start (BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE)
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#define ext_irq_end (BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE)
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#define ext_irq_count 4
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#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6328
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#define ext_irq_cfg_reg2 0
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6338
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#define irq_stat_reg PERF_IRQSTAT_6338_REG
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#define irq_mask_reg PERF_IRQMASK_6338_REG
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@ -118,6 +129,16 @@ static void bcm63xx_init_irq(void)
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irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
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switch (bcm63xx_get_cpu_id()) {
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case BCM6328_CPU_ID:
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irq_stat_addr += PERF_IRQSTAT_6328_REG;
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irq_mask_addr += PERF_IRQMASK_6328_REG;
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irq_bits = 64;
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ext_irq_count = 4;
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is_ext_irq_cascaded = 1;
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ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;
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ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;
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ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
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break;
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case BCM6338_CPU_ID:
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irq_stat_addr += PERF_IRQSTAT_6338_REG;
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irq_mask_addr += PERF_IRQMASK_6338_REG;
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@ -26,7 +26,9 @@ void __init prom_init(void)
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bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG);
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/* disable all hardware blocks clock for now */
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if (BCMCPU_IS_6338())
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if (BCMCPU_IS_6328())
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mask = CKCTL_6328_ALL_SAFE_EN;
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else if (BCMCPU_IS_6338())
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mask = CKCTL_6338_ALL_SAFE_EN;
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else if (BCMCPU_IS_6345())
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mask = CKCTL_6345_ALL_SAFE_EN;
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@ -68,6 +68,9 @@ void bcm63xx_machine_reboot(void)
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/* mask and clear all external irq */
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switch (bcm63xx_get_cpu_id()) {
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case BCM6328_CPU_ID:
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perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328;
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break;
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case BCM6338_CPU_ID:
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perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338;
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break;
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@ -95,9 +98,13 @@ void bcm63xx_machine_reboot(void)
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bcm6348_a1_reboot();
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printk(KERN_INFO "triggering watchdog soft-reset...\n");
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reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG);
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reg |= SYS_PLL_SOFT_RESET;
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bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG);
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if (BCMCPU_IS_6328()) {
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bcm_wdt_writel(1, WDT_SOFTRESET_REG);
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} else {
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reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG);
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reg |= SYS_PLL_SOFT_RESET;
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bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG);
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}
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while (1)
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;
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}
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@ -9,6 +9,7 @@
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* compile time if only one CPU support is enabled (idea stolen from
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* arm mach-types)
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*/
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#define BCM6328_CPU_ID 0x6328
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#define BCM6338_CPU_ID 0x6338
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#define BCM6345_CPU_ID 0x6345
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#define BCM6348_CPU_ID 0x6348
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@ -20,6 +21,19 @@ u16 __bcm63xx_get_cpu_id(void);
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u16 bcm63xx_get_cpu_rev(void);
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unsigned int bcm63xx_get_cpu_freq(void);
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#ifdef CONFIG_BCM63XX_CPU_6328
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# ifdef bcm63xx_get_cpu_id
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# undef bcm63xx_get_cpu_id
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# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
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# define BCMCPU_RUNTIME_DETECT
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# else
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# define bcm63xx_get_cpu_id() BCM6328_CPU_ID
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# endif
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# define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
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#else
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# define BCMCPU_IS_6328() (0)
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6338
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# ifdef bcm63xx_get_cpu_id
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# undef bcm63xx_get_cpu_id
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@ -129,7 +143,8 @@ enum bcm63xx_regs_set {
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RSET_PCMDMA,
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RSET_PCMDMAC,
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RSET_PCMDMAS,
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RSET_RNG
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RSET_RNG,
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RSET_MISC
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};
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#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
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@ -155,6 +170,49 @@ enum bcm63xx_regs_set {
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#define RSET_XTMDMAS_SIZE(chans) (16 * (chans))
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#define RSET_RNG_SIZE 20
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/*
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* 6328 register sets base address
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*/
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#define BCM_6328_DSL_LMEM_BASE (0xdeadbeef)
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#define BCM_6328_PERF_BASE (0xb0000000)
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#define BCM_6328_TIMER_BASE (0xb0000040)
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#define BCM_6328_WDT_BASE (0xb000005c)
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#define BCM_6328_UART0_BASE (0xb0000100)
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#define BCM_6328_UART1_BASE (0xb0000120)
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#define BCM_6328_GPIO_BASE (0xb0000080)
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#define BCM_6328_SPI_BASE (0xdeadbeef)
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#define BCM_6328_UDC0_BASE (0xdeadbeef)
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#define BCM_6328_USBDMA_BASE (0xdeadbeef)
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#define BCM_6328_OHCI0_BASE (0xdeadbeef)
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#define BCM_6328_OHCI_PRIV_BASE (0xdeadbeef)
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#define BCM_6328_USBH_PRIV_BASE (0xdeadbeef)
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#define BCM_6328_MPI_BASE (0xdeadbeef)
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#define BCM_6328_PCMCIA_BASE (0xdeadbeef)
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#define BCM_6328_SDRAM_REGS_BASE (0xdeadbeef)
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#define BCM_6328_DSL_BASE (0xb0001900)
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#define BCM_6328_UBUS_BASE (0xdeadbeef)
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#define BCM_6328_ENET0_BASE (0xdeadbeef)
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#define BCM_6328_ENET1_BASE (0xdeadbeef)
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#define BCM_6328_ENETDMA_BASE (0xb000d800)
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#define BCM_6328_ENETDMAC_BASE (0xb000da00)
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#define BCM_6328_ENETDMAS_BASE (0xb000dc00)
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#define BCM_6328_ENETSW_BASE (0xb0e00000)
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#define BCM_6328_EHCI0_BASE (0x10002500)
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#define BCM_6328_SDRAM_BASE (0xdeadbeef)
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#define BCM_6328_MEMC_BASE (0xdeadbeef)
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#define BCM_6328_DDR_BASE (0xb0003000)
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#define BCM_6328_M2M_BASE (0xdeadbeef)
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#define BCM_6328_ATM_BASE (0xdeadbeef)
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#define BCM_6328_XTM_BASE (0xdeadbeef)
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#define BCM_6328_XTMDMA_BASE (0xb000b800)
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#define BCM_6328_XTMDMAC_BASE (0xdeadbeef)
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#define BCM_6328_XTMDMAS_BASE (0xdeadbeef)
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#define BCM_6328_PCM_BASE (0xb000a800)
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#define BCM_6328_PCMDMA_BASE (0xdeadbeef)
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#define BCM_6328_PCMDMAC_BASE (0xdeadbeef)
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#define BCM_6328_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_6328_RNG_BASE (0xdeadbeef)
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#define BCM_6328_MISC_BASE (0xb0001800)
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/*
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* 6338 register sets base address
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*/
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@ -198,6 +256,7 @@ enum bcm63xx_regs_set {
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#define BCM_6338_PCMDMAC_BASE (0xdeadbeef)
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#define BCM_6338_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_6338_RNG_BASE (0xdeadbeef)
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#define BCM_6338_MISC_BASE (0xdeadbeef)
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/*
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* 6345 register sets base address
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@ -242,6 +301,7 @@ enum bcm63xx_regs_set {
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#define BCM_6345_PCMDMAC_BASE (0xdeadbeef)
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#define BCM_6345_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_6345_RNG_BASE (0xdeadbeef)
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#define BCM_6345_MISC_BASE (0xdeadbeef)
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/*
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* 6348 register sets base address
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@ -283,6 +343,7 @@ enum bcm63xx_regs_set {
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#define BCM_6348_PCMDMAC_BASE (0xdeadbeef)
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#define BCM_6348_PCMDMAS_BASE (0xdeadbeef)
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#define BCM_6348_RNG_BASE (0xdeadbeef)
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#define BCM_6348_MISC_BASE (0xdeadbeef)
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/*
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* 6358 register sets base address
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@ -324,6 +385,7 @@ enum bcm63xx_regs_set {
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#define BCM_6358_PCMDMAC_BASE (0xfffe1900)
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#define BCM_6358_PCMDMAS_BASE (0xfffe1a00)
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#define BCM_6358_RNG_BASE (0xdeadbeef)
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#define BCM_6358_MISC_BASE (0xdeadbeef)
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/*
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@ -366,6 +428,7 @@ enum bcm63xx_regs_set {
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#define BCM_6368_PCMDMAC_BASE (0xb0005a00)
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#define BCM_6368_PCMDMAS_BASE (0xb0005c00)
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#define BCM_6368_RNG_BASE (0xb0004180)
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#define BCM_6368_MISC_BASE (0xdeadbeef)
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extern const unsigned long *bcm63xx_regs_base;
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@ -412,6 +475,7 @@ extern const unsigned long *bcm63xx_regs_base;
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__GEN_RSET_BASE(__cpu, PCMDMAC) \
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__GEN_RSET_BASE(__cpu, PCMDMAS) \
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__GEN_RSET_BASE(__cpu, RNG) \
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__GEN_RSET_BASE(__cpu, MISC) \
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}
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#define __GEN_CPU_REGS_TABLE(__cpu) \
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@ -451,6 +515,7 @@ extern const unsigned long *bcm63xx_regs_base;
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[RSET_PCMDMAC] = BCM_## __cpu ##_PCMDMAC_BASE, \
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[RSET_PCMDMAS] = BCM_## __cpu ##_PCMDMAS_BASE, \
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[RSET_RNG] = BCM_## __cpu ##_RNG_BASE, \
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[RSET_MISC] = BCM_## __cpu ##_MISC_BASE, \
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static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
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@ -458,6 +523,9 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
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#ifdef BCMCPU_RUNTIME_DETECT
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return bcm63xx_regs_base[set];
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#else
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#ifdef CONFIG_BCM63XX_CPU_6328
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__GEN_RSET(6328)
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#endif
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#ifdef CONFIG_BCM63XX_CPU_6338
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__GEN_RSET(6338)
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#endif
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@ -511,6 +579,47 @@ enum bcm63xx_irq {
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IRQ_XTM_DMA0,
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};
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/*
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* 6328 irqs
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*/
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#define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
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#define BCM_6328_TIMER_IRQ (IRQ_INTERNAL_BASE + 31)
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#define BCM_6328_SPI_IRQ 0
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#define BCM_6328_UART0_IRQ (IRQ_INTERNAL_BASE + 28)
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#define BCM_6328_UART1_IRQ (BCM_6328_HIGH_IRQ_BASE + 7)
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#define BCM_6328_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
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#define BCM_6328_UDC0_IRQ 0
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#define BCM_6328_ENET0_IRQ 0
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#define BCM_6328_ENET1_IRQ 0
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#define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
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#define BCM_6328_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9)
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#define BCM_6328_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
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#define BCM_6328_PCMCIA_IRQ 0
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#define BCM_6328_ENET0_RXDMA_IRQ 0
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#define BCM_6328_ENET0_TXDMA_IRQ 0
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||||
#define BCM_6328_ENET1_RXDMA_IRQ 0
|
||||
#define BCM_6328_ENET1_TXDMA_IRQ 0
|
||||
#define BCM_6328_PCI_IRQ (IRQ_INTERNAL_BASE + 23)
|
||||
#define BCM_6328_ATM_IRQ 0
|
||||
#define BCM_6328_ENETSW_RXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 0)
|
||||
#define BCM_6328_ENETSW_RXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 1)
|
||||
#define BCM_6328_ENETSW_RXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 2)
|
||||
#define BCM_6328_ENETSW_RXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 3)
|
||||
#define BCM_6328_ENETSW_TXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 4)
|
||||
#define BCM_6328_ENETSW_TXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 5)
|
||||
#define BCM_6328_ENETSW_TXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 6)
|
||||
#define BCM_6328_ENETSW_TXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 7)
|
||||
#define BCM_6328_XTM_IRQ (BCM_6328_HIGH_IRQ_BASE + 31)
|
||||
#define BCM_6328_XTM_DMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 11)
|
||||
|
||||
#define BCM_6328_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 2)
|
||||
#define BCM_6328_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 3)
|
||||
#define BCM_6328_EXT_IRQ0 (IRQ_INTERNAL_BASE + 24)
|
||||
#define BCM_6328_EXT_IRQ1 (IRQ_INTERNAL_BASE + 25)
|
||||
#define BCM_6328_EXT_IRQ2 (IRQ_INTERNAL_BASE + 26)
|
||||
#define BCM_6328_EXT_IRQ3 (IRQ_INTERNAL_BASE + 27)
|
||||
|
||||
/*
|
||||
* 6338 irqs
|
||||
*/
|
||||
|
||||
@ -9,6 +9,8 @@ int __init bcm63xx_gpio_init(void);
|
||||
static inline unsigned long bcm63xx_gpio_count(void)
|
||||
{
|
||||
switch (bcm63xx_get_cpu_id()) {
|
||||
case BCM6328_CPU_ID:
|
||||
return 32;
|
||||
case BCM6358_CPU_ID:
|
||||
return 40;
|
||||
case BCM6338_CPU_ID:
|
||||
|
||||
@ -91,5 +91,7 @@
|
||||
#define bcm_memc_writel(v, o) bcm_rset_writel(RSET_MEMC, (v), (o))
|
||||
#define bcm_ddr_readl(o) bcm_rset_readl(RSET_DDR, (o))
|
||||
#define bcm_ddr_writel(v, o) bcm_rset_writel(RSET_DDR, (v), (o))
|
||||
#define bcm_misc_readl(o) bcm_rset_readl(RSET_MISC, (o))
|
||||
#define bcm_misc_writel(v, o) bcm_rset_writel(RSET_MISC, (v), (o))
|
||||
|
||||
#endif /* ! BCM63XX_IO_H_ */
|
||||
|
||||
@ -15,6 +15,30 @@
|
||||
/* Clock Control register */
|
||||
#define PERF_CKCTL_REG 0x4
|
||||
|
||||
#define CKCTL_6328_PHYMIPS_EN (1 << 0)
|
||||
#define CKCTL_6328_ADSL_QPROC_EN (1 << 1)
|
||||
#define CKCTL_6328_ADSL_AFE_EN (1 << 2)
|
||||
#define CKCTL_6328_ADSL_EN (1 << 3)
|
||||
#define CKCTL_6328_MIPS_EN (1 << 4)
|
||||
#define CKCTL_6328_SAR_EN (1 << 5)
|
||||
#define CKCTL_6328_PCM_EN (1 << 6)
|
||||
#define CKCTL_6328_USBD_EN (1 << 7)
|
||||
#define CKCTL_6328_USBH_EN (1 << 8)
|
||||
#define CKCTL_6328_HSSPI_EN (1 << 9)
|
||||
#define CKCTL_6328_PCIE_EN (1 << 10)
|
||||
#define CKCTL_6328_ROBOSW_EN (1 << 11)
|
||||
|
||||
#define CKCTL_6328_ALL_SAFE_EN (CKCTL_6328_PHYMIPS_EN | \
|
||||
CKCTL_6328_ADSL_QPROC_EN | \
|
||||
CKCTL_6328_ADSL_AFE_EN | \
|
||||
CKCTL_6328_ADSL_EN | \
|
||||
CKCTL_6328_SAR_EN | \
|
||||
CKCTL_6328_PCM_EN | \
|
||||
CKCTL_6328_USBD_EN | \
|
||||
CKCTL_6328_USBH_EN | \
|
||||
CKCTL_6328_ROBOSW_EN | \
|
||||
CKCTL_6328_PCIE_EN)
|
||||
|
||||
#define CKCTL_6338_ADSLPHY_EN (1 << 0)
|
||||
#define CKCTL_6338_MPI_EN (1 << 1)
|
||||
#define CKCTL_6338_DRAM_EN (1 << 2)
|
||||
@ -119,6 +143,7 @@
|
||||
#define SYS_PLL_SOFT_RESET 0x1
|
||||
|
||||
/* Interrupt Mask register */
|
||||
#define PERF_IRQMASK_6328_REG 0x20
|
||||
#define PERF_IRQMASK_6338_REG 0xc
|
||||
#define PERF_IRQMASK_6345_REG 0xc
|
||||
#define PERF_IRQMASK_6348_REG 0xc
|
||||
@ -126,6 +151,7 @@
|
||||
#define PERF_IRQMASK_6368_REG 0x20
|
||||
|
||||
/* Interrupt Status register */
|
||||
#define PERF_IRQSTAT_6328_REG 0x28
|
||||
#define PERF_IRQSTAT_6338_REG 0x10
|
||||
#define PERF_IRQSTAT_6345_REG 0x10
|
||||
#define PERF_IRQSTAT_6348_REG 0x10
|
||||
@ -133,6 +159,7 @@
|
||||
#define PERF_IRQSTAT_6368_REG 0x28
|
||||
|
||||
/* External Interrupt Configuration register */
|
||||
#define PERF_EXTIRQ_CFG_REG_6328 0x18
|
||||
#define PERF_EXTIRQ_CFG_REG_6338 0x14
|
||||
#define PERF_EXTIRQ_CFG_REG_6348 0x14
|
||||
#define PERF_EXTIRQ_CFG_REG_6358 0x14
|
||||
@ -162,8 +189,21 @@
|
||||
|
||||
/* Soft Reset register */
|
||||
#define PERF_SOFTRESET_REG 0x28
|
||||
#define PERF_SOFTRESET_6328_REG 0x10
|
||||
#define PERF_SOFTRESET_6368_REG 0x10
|
||||
|
||||
#define SOFTRESET_6328_SPI_MASK (1 << 0)
|
||||
#define SOFTRESET_6328_EPHY_MASK (1 << 1)
|
||||
#define SOFTRESET_6328_SAR_MASK (1 << 2)
|
||||
#define SOFTRESET_6328_ENETSW_MASK (1 << 3)
|
||||
#define SOFTRESET_6328_USBS_MASK (1 << 4)
|
||||
#define SOFTRESET_6328_USBH_MASK (1 << 5)
|
||||
#define SOFTRESET_6328_PCM_MASK (1 << 6)
|
||||
#define SOFTRESET_6328_PCIE_CORE_MASK (1 << 7)
|
||||
#define SOFTRESET_6328_PCIE_MASK (1 << 8)
|
||||
#define SOFTRESET_6328_PCIE_EXT_MASK (1 << 9)
|
||||
#define SOFTRESET_6328_PCIE_HARD_MASK (1 << 10)
|
||||
|
||||
#define SOFTRESET_6338_SPI_MASK (1 << 0)
|
||||
#define SOFTRESET_6338_ENET_MASK (1 << 2)
|
||||
#define SOFTRESET_6338_USBH_MASK (1 << 3)
|
||||
@ -307,6 +347,8 @@
|
||||
/* Watchdog reset length register */
|
||||
#define WDT_RSTLEN_REG 0x8
|
||||
|
||||
/* Watchdog soft reset register (BCM6328 only) */
|
||||
#define WDT_SOFTRESET_REG 0xc
|
||||
|
||||
/*************************************************************************
|
||||
* _REG relative to RSET_UARTx
|
||||
@ -933,6 +975,8 @@
|
||||
* _REG relative to RSET_DDR
|
||||
*************************************************************************/
|
||||
|
||||
#define DDR_CSEND_REG 0x8
|
||||
|
||||
#define DDR_DMIPSPLLCFG_REG 0x18
|
||||
#define DMIPSPLLCFG_M1_SHIFT 0
|
||||
#define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT)
|
||||
@ -1115,4 +1159,14 @@
|
||||
#define SPI_SSOFFTIME_SHIFT 3
|
||||
#define SPI_BYTE_SWAP 0x80
|
||||
|
||||
/*************************************************************************
|
||||
* _REG relative to RSET_MISC
|
||||
*************************************************************************/
|
||||
|
||||
#define MISC_STRAPBUS_6328_REG 0x240
|
||||
#define STRAPBUS_6328_FCVO_SHIFT 7
|
||||
#define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
|
||||
#define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28)
|
||||
#define STRAPBUS_6328_BOOT_SEL_NAND (0 << 28)
|
||||
|
||||
#endif /* BCM63XX_REGS_H_ */
|
||||
|
||||
@ -18,6 +18,7 @@ static inline int is_bcm63xx_internal_registers(phys_t offset)
|
||||
if (offset >= 0xfff00000)
|
||||
return 1;
|
||||
break;
|
||||
case BCM6328_CPU_ID:
|
||||
case BCM6368_CPU_ID:
|
||||
if (offset >= 0xb0000000 && offset < 0xb1000000)
|
||||
return 1;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user